[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 8/8] fdc-test: Test state for existing cases more
From: |
Kevin Wolf |
Subject: |
[Qemu-devel] [PATCH v2 8/8] fdc-test: Test state for existing cases more thoroughly |
Date: |
Thu, 21 May 2015 15:19:38 +0200 |
This just adds a few additional checks of the MSR and interrupt pin to
the already existing test cases.
Signed-off-by: Kevin Wolf <address@hidden>
Reviewed-by: John Snow <address@hidden>
---
tests/fdc-test.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tests/fdc-test.c b/tests/fdc-test.c
index 3c6c83c..416394f 100644
--- a/tests/fdc-test.c
+++ b/tests/fdc-test.c
@@ -218,6 +218,10 @@ static uint8_t send_read_no_dma_command(int nb_sect,
uint8_t expected_st0)
inb(FLOPPY_BASE + reg_fifo);
}
+ msr = inb(FLOPPY_BASE + reg_msr);
+ assert_bit_set(msr, BUSY | RQM | DIO);
+ g_assert(get_irq(FLOPPY_IRQ));
+
st0 = floppy_recv();
if (st0 != expected_st0) {
ret = 1;
@@ -228,8 +232,15 @@ static uint8_t send_read_no_dma_command(int nb_sect,
uint8_t expected_st0)
floppy_recv();
floppy_recv();
floppy_recv();
+ g_assert(get_irq(FLOPPY_IRQ));
floppy_recv();
+ /* Check that we're back in command phase */
+ msr = inb(FLOPPY_BASE + reg_msr);
+ assert_bit_clear(msr, BUSY | DIO);
+ assert_bit_set(msr, RQM);
+ g_assert(!get_irq(FLOPPY_IRQ));
+
return ret;
}
@@ -403,6 +414,7 @@ static void test_read_id(void)
uint8_t head = 0;
uint8_t cyl;
uint8_t st0;
+ uint8_t msr;
/* Seek to track 0 and check with READ ID */
send_seek(0);
@@ -411,18 +423,29 @@ static void test_read_id(void)
g_assert(!get_irq(FLOPPY_IRQ));
floppy_send(head << 2 | drive);
+ msr = inb(FLOPPY_BASE + reg_msr);
+ if (!get_irq(FLOPPY_IRQ)) {
+ assert_bit_set(msr, BUSY);
+ assert_bit_clear(msr, RQM);
+ }
+
while (!get_irq(FLOPPY_IRQ)) {
/* qemu involves a timer with READ ID... */
clock_step(1000000000LL / 50);
}
+ msr = inb(FLOPPY_BASE + reg_msr);
+ assert_bit_set(msr, BUSY | RQM | DIO);
+
st0 = floppy_recv();
floppy_recv();
floppy_recv();
cyl = floppy_recv();
head = floppy_recv();
floppy_recv();
+ g_assert(get_irq(FLOPPY_IRQ));
floppy_recv();
+ g_assert(!get_irq(FLOPPY_IRQ));
g_assert_cmpint(cyl, ==, 0);
g_assert_cmpint(head, ==, 0);
@@ -443,18 +466,29 @@ static void test_read_id(void)
g_assert(!get_irq(FLOPPY_IRQ));
floppy_send(head << 2 | drive);
+ msr = inb(FLOPPY_BASE + reg_msr);
+ if (!get_irq(FLOPPY_IRQ)) {
+ assert_bit_set(msr, BUSY);
+ assert_bit_clear(msr, RQM);
+ }
+
while (!get_irq(FLOPPY_IRQ)) {
/* qemu involves a timer with READ ID... */
clock_step(1000000000LL / 50);
}
+ msr = inb(FLOPPY_BASE + reg_msr);
+ assert_bit_set(msr, BUSY | RQM | DIO);
+
st0 = floppy_recv();
floppy_recv();
floppy_recv();
cyl = floppy_recv();
head = floppy_recv();
floppy_recv();
+ g_assert(get_irq(FLOPPY_IRQ));
floppy_recv();
+ g_assert(!get_irq(FLOPPY_IRQ));
g_assert_cmpint(cyl, ==, 8);
g_assert_cmpint(head, ==, 1);
--
1.8.3.1
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, (continued)
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Dr. David Alan Gilbert, 2015/05/28
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Markus Armbruster, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Dr. David Alan Gilbert, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Kevin Wolf, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Dr. David Alan Gilbert, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Kevin Wolf, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Dr. David Alan Gilbert, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Peter Maydell, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Dr. David Alan Gilbert, 2015/05/29
- Re: [Qemu-devel] [PATCH v2 3/8] fdc: Introduce fdctrl->phase, Kevin Wolf, 2015/05/29
[Qemu-devel] [PATCH v2 8/8] fdc-test: Test state for existing cases more thoroughly,
Kevin Wolf <=