Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

[Richard Henderson]

On 05/14/2015 02:46 AM, Yongbok Kim wrote:
> In addition to that, if we issue all the loads let say only the first page is
> accessible, in the architectural point of view it would be fine as nothing 
> will
> be stored in the vector register but accessing the first page is "visible" 
> from
> the data bus.
> Do you think this wouldn't cause any problem?
> It might be just implementation dependent though.

I don't think it would cause a problem unless the user is silly enough to issue
an MSA read to device memory.


r~