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Re: [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_s
From: |
alvise rigo |
Subject: |
Re: [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions |
Date: |
Mon, 11 May 2015 10:12:28 +0200 |
On Thu, May 7, 2015 at 7:58 PM, Richard Henderson <address@hidden> wrote:
> On 05/06/2015 08:38 AM, Alvise Rigo wrote:
>> +/* An output operand to return the StoreConditional result */
>> +static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val,
>> + TCGv addr, TCGMemOp memop, TCGArg idx)
>> +{
>> + tcg_gen_op5ii_i32(opc, is_dirty, val, addr, memop, idx);
>> +}
>
> This is the wrong way to go about this. I think you should merely add an EXCL
> bit to TCGMemOp, and add no new opcodes at all.
You are right, there is no need of a new opcode here.
Thank you,
alvise
>
>
> r~
- [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Alvise Rigo, 2015/05/06
- [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list, Alvise Rigo, 2015/05/06
- [Qemu-devel] [RFC 2/5] Add new TLB_EXCL flag, Alvise Rigo, 2015/05/06
- [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions, Alvise Rigo, 2015/05/06
- [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path, Alvise Rigo, 2015/05/06
- [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops, Alvise Rigo, 2015/05/06
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Paolo Bonzini, 2015/05/06
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Mark Burton, 2015/05/06