[Qemu-devel] [RFC PATCH 14/34] mb: Use qomified tcg defintions

[Peter Crosthwaite]

Prepare support for multi-arch. TCG core code will have to get the
architecture specific variant of these definitions.

Signed-off-by: Peter Crosthwaite <address@hidden>
---
 target-microblaze/cpu.c       | 34 ++++++++++++++++++++++++++++++++++
 target-microblaze/cpu.h       | 32 ++++++++++++--------------------
 target-microblaze/op_helper.c |  4 ++--
 target-microblaze/translate.c |  8 +++++---
 4 files changed, 53 insertions(+), 25 deletions(-)

diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 89b8363..4e5489e 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -54,6 +54,31 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, 
int level)
 }
 #endif
 
+static int mb_cpu_mmu_index (CPUState *cpu) {
+    CPUMBState *env = cpu->env_ptr;
+
+    /* Are we in nommu mode?.  */
+    if (!(env->sregs[SR_MSR] & MSR_VM))
+        return MMU_NOMMU_IDX;
+
+       if (env->sregs[SR_MSR] & MSR_UM)
+            return MMU_USER_IDX;
+        return MMU_KERNEL_IDX;
+}
+
+static void mb_cpu_get_tb_cpu_state(CPUState *cpu, void *pc_ptr,
+                                    void *cs_base_ptr, int *flags)
+{
+    CPUMBState *env = cpu->env_ptr;
+    target_ulong *pc = pc_ptr;
+    target_ulong *cs_base = cs_base_ptr;
+
+    *pc = env->sregs[SR_PC];
+    *cs_base = 0;
+    *flags = (env->iflags & IFLAGS_TB_MASK) |
+                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
+}
+
 /* CPUClass::reset() */
 static void mb_cpu_reset(CPUState *s)
 {
@@ -191,6 +216,15 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_num_core_regs = 32 + 5;
 
     cc->disas_set_info = mb_disas_set_info;
+
+    cc->cpu_mmu_index = mb_cpu_mmu_index;
+    cc->cpu_get_tb_cpu_state = mb_cpu_get_tb_cpu_state;
+    cc->gen_intermediate_code = mb_gen_intermediate_code;
+    cc->gen_intermediate_code_pc = mb_gen_intermediate_code_pc;
+    cc->restore_state_to_opc = mb_restore_state_to_opc;
+#ifndef CONFIG_USER_ONLY
+    cc->tlb_fill = mb_tlb_fill;
+#endif
 }
 
 static const TypeInfo mb_cpu_type_info = {
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 51a49f2..bcaff1f 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -289,36 +289,28 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
 #define MMU_USER_IDX    2
 /* See NB_MMU_MODES further up the file.  */
 
-static inline int cpu_mmu_index (CPUMBState *env)
-{
-        /* Are we in nommu mode?.  */
-        if (!(env->sregs[SR_MSR] & MSR_VM))
-            return MMU_NOMMU_IDX;
-
-       if (env->sregs[SR_MSR] & MSR_UM)
-            return MMU_USER_IDX;
-        return MMU_KERNEL_IDX;
-}
-
 int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
                             int mmu_idx);
 
-static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
-                                        target_ulong *cs_base, int *flags)
-{
-    *pc = env->sregs[SR_PC];
-    *cs_base = 0;
-    *flags = (env->iflags & IFLAGS_TB_MASK) |
-                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
-}
-
 #if !defined(CONFIG_USER_ONLY)
 void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
                               bool is_write, bool is_exec, int is_asi,
                               unsigned size);
 #endif
 
+#define cpu_get_tb_cpu_state(env, pc, cs_base, flags) \
+    (ENV_GET_CPU(env)->cpu_get_tb_cpu_state(ENV_GET_CPU(env), (pc), \
+                                            (cs_base), (flags)))
+
+#define cpu_mmu_index(env) (ENV_GET_CPU(env)->cpu_mmu_index(ENV_GET_CPU(env)))
+
 #include "exec/cpu-all.h"
 #include "exec/exec-all.h"
 
+void mb_gen_intermediate_code(void *env, struct TranslationBlock *tb);
+void mb_gen_intermediate_code_pc(void *env, struct TranslationBlock *tb);
+void mb_restore_state_to_opc(void *env_ptr, TranslationBlock *tb, int pc_pos);
+void mb_tlb_fill(CPUState *cs, uint64_t addr, int is_write, int mmu_idx,
+                 uintptr_t retaddr);
+
 #endif
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index df2d74f..1fceb24 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -32,8 +32,8 @@
  * NULL, it means that the function was called in C code (i.e. not
  * from generated code or from helper.c)
  */
-void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
-              uintptr_t retaddr)
+void mb_tlb_fill(CPUState *cs, uint64_t addr, int is_write, int mmu_idx,
+                 uintptr_t retaddr)
 {
     int ret;
 
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index ec655fd..88b35ff 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1878,12 +1878,12 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, 
TranslationBlock *tb,
     assert(!dc->abort_at_next_insn);
 }
 
-void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
+void mb_gen_intermediate_code(void *env, struct TranslationBlock *tb)
 {
     gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
 }
 
-void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
+void mb_gen_intermediate_code_pc(void *env, struct TranslationBlock *tb)
 {
     gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
 }
@@ -1968,7 +1968,9 @@ void mb_tcg_init(void)
     }
 }
 
-void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
+void mb_restore_state_to_opc(void *env_ptr, TranslationBlock *tb, int pc_pos)
 {
+    CPUMBState *env = env_ptr;
+
     env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
 }
-- 
1.9.1