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[Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external R
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external RAM |
Date: |
Wed, 6 May 2015 15:50:29 -0700 |
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size clamps and warnings
hw/arm/xlnx-ep108.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 81704bb..46f145b 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -18,11 +18,16 @@
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
typedef struct XlnxEP108 {
XlnxZynqMPState soc;
+ MemoryRegion ddr_ram;
} XlnxEP108;
+/* Max 2GB RAM */
+#define EP108_MAX_RAM_SIZE 0x80000000ull
+
static void xlnx_ep108_init(MachineState *machine)
{
XlnxEP108 *s = g_new0(XlnxEP108, 1);
@@ -37,6 +42,21 @@ static void xlnx_ep108_init(MachineState *machine)
error_report("%s", error_get_pretty(err));
exit(1);
}
+
+ if (machine->ram_size > EP108_MAX_RAM_SIZE) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
+ "reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
+ machine->ram_size = EP108_MAX_RAM_SIZE;
+ }
+
+ if (machine->ram_size <= 0x08000000) {
+ qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
+ machine->ram_size);
+ }
+
+ memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
+ machine->ram_size);
+ memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
}
static QEMUMachine xlnx_ep108_machine = {
--
2.4.0.3.ge0ccc3b.dirty
- [Qemu-devel] [PATCH target-arm v7 03/15] arm: Introduce Xilinx ZynqMP SoC, (continued)
- [Qemu-devel] [PATCH target-arm v7 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 13/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 08/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 15/15] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 11/15] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 09/15] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external RAM,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v7 07/15] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 10/15] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 12/15] arm: xlnx-zynqmp: Add UART support, Peter Crosthwaite, 2015/05/06
- Re: [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC, Peter Maydell, 2015/05/07