Re: [Qemu-devel] [PATCH 2/3] target-mips: Misaligned Memory Accesses for R6

[Peter Maydell]

On 1 May 2015 at 16:24, Yongbok Kim <address@hidden> wrote:
> Release 6 requires misaligned memory access support for all ordinary memory
> access instructions (for example, LW/SW, LWC1/SWC1).
> However misaligned support is not provided for certain special memory accesses
> such as atomics (for example, LL/SC).
>
> In the mips_cpu_do_unaligned_access() callback, if it is R6 core it checks 
> further
> whether the address is valid.
>
> Signed-off-by: Yongbok Kim <address@hidden>
> ---
>  target-mips/cpu.h            |    2 ++
>  target-mips/helper.c         |   36 ++++++++++++++++++++++++++++++++++++
>  target-mips/op_helper.c      |   13 +++++++++++++
>  target-mips/translate_init.c |    2 +-
>  4 files changed, 52 insertions(+), 1 deletions(-)
>
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index f9d2b4c..6586d89 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -760,6 +760,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr 
> address, int rw,
>  void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
>  hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
>                                                int rw);
> +bool cpu_mips_validate_access(CPUMIPSState *env, target_ulong address,
> +                            target_ulong badvaddr, unsigned data_size, int 
> rw);
>  #endif
>  target_ulong exception_resume_pc (CPUMIPSState *env);
>
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index 8e3204a..6c44124 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -391,6 +391,42 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, 
> target_ulong address, int r
>      }
>  }
>
> +bool cpu_mips_validate_access(CPUMIPSState *env, target_ulong address,
> +                            target_ulong badvaddr, unsigned data_size, int 
> rw)
> +{
> +    hwaddr physical;
> +    int prot;
> +    int access_type = ACCESS_INT;
> +    int ret;
> +    target_ulong addr;
> +
> +    addr = address & ~((target_ulong) data_size - 1);
> +    ret = get_physical_address(env, &physical, &prot,
> +            addr, rw, access_type);

Isn't a recheck of the TLB on every unaligned access going
to have poor performance? If we know from the type of the
insn whether an unaligned access is OK or not there ought
to be some way to avoid doing the check at all...

-- PMM