[Qemu-devel] [PATCH] target-ppc: don't invalidate msr MSR_HVB bit in cpu_post_load

[Mark Cave-Ayland]

The invalidation code introduced in commit 2360b works by inverting most bits
of env->msr to ensure that hreg_store_msr() will forcibly update the CPU env
state to reflect the new msr value post-migration. Unfortunately
hreg_store_msr() is called with alter_hv set to 0 which preserves the MSR_HVB
state from the CPU env which is now the opposite value to what it should be.

Ensure that we don't invalidate the msr MSR_HVB bit during cpu_post_load so
that the correct value is restored. This fixes suspend/resume for PPC64.

Reported-by: Stefan Berger <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
 target-ppc/machine.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 3921012..d875211 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -192,9 +192,9 @@ static int cpu_post_load(void *opaque, int version_id)
         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
     }
 
-    /* Mark msr bits except MSR_TGPR invalid before restoring */
+    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
     msr = env->msr;
-    env->msr ^= ~(1ULL << MSR_TGPR);
+    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
     ppc_store_msr(env, msr);
 
     hreg_compute_mem_idx(env);
-- 
1.7.10.4