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Re: [Qemu-devel] [[PATCH] 3/7] target-arm: Update interrupt handling to


From: Greg Bellows
Subject: Re: [Qemu-devel] [[PATCH] 3/7] target-arm: Update interrupt handling to use target EL
Date: Thu, 16 Apr 2015 16:03:37 -0500



On Thu, Apr 16, 2015 at 12:52 PM, Peter Maydell <address@hidden> wrote:
On 27 March 2015 at 19:10, Greg Bellows <address@hidden> wrote:
> Updated the interrupt handling to utilize and report through the target EL
> exception field.  This includes consolidating and cleaning up code where
> needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and
> do_interrupt was updated to use the target_el exception field.  The
> necessary code from arm_excp_target_el() was merged in where needed and the
> function removed.

> --- a/target-arm/helper-a64.c
> +++ b/target-arm/helper-a64.c
> @@ -463,7 +463,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
>  {
>      ARMCPU *cpu = ARM_CPU(cs);
>      CPUARMState *env = &cpu->env;
> -    unsigned int new_el = arm_excp_target_el(cs, cs->exception_index);
> +    unsigned int new_el = MAX(env->exception.target_el, 1);

Surely we should never be able to get here with target_el zero?

​Ideally that would be true and I wondered that myself so I took out the the MAX safety net in arm_excp_target_el() and later hit the assert in aarch64_banked_spsr_index() because new_el was 0.  This is why I preserved the MAX behavior everywhere because just like the original code, there are cases where current_el is 0.

​I figured this was the safest alternative as it would catch all the cases where we were not specifying the target EL.  


Rest of the patch looks OK.

-- PMM


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