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Re: [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping |
Date: |
Tue, 14 Apr 2015 20:18:56 +0100 |
On 30 October 2014 at 22:11, Greg Bellows <address@hidden> wrote:
> This patch series adds ARM GICv1 and GICv2 security extension support. As a
> result GIC interrupt grouping and FIQ enablement have also been added. FIQ
> enablement is limited to ARM the ARM vexpress and virt machines.
>
> At the current moment, the security extension capability is not enabled as it
> depends on ARM secure address space support for proper operation. Instead,
> secure checks are hardwired as non-secure.
Hi Greg -- just noticed you forgot to add your own signed-off-by:
tag to these patches (needed as well as Fabian's since they passed
through your hands). Could you reply to this cover letter giving it,
please?
thanks
-- PMM
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