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Re: [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect C
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC |
Date: |
Mon, 30 Mar 2015 11:29:31 +1000 |
On Mon, Mar 23, 2015 at 9:05 PM, Peter Crosthwaite
<address@hidden> wrote:
> Connect the GPIO outputs from the individual CPUs for the timers to the
> GIC.
>
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
> hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 9465185..29954f5 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -19,9 +19,17 @@
>
> #define GIC_NUM_SPI_INTR 128
>
> +#define ARM_PHYS_TIMER_PPI 30
> +#define ARM_VIRT_TIMER_PPI 27
> +
> #define GIC_DIST_ADDR 0xf9010000
> #define GIC_CPU_ADDR 0xf9020000
Hey Peter,
I'm wondering if the #define's should be in the header file?
>
> +static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
> +{
> + return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
Should the 32 also be a #define? Everything else is.
Thanks,
Alistair
> +}
> +
> static void xlnx_zynqmp_init(Object *obj)
> {
> XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
> @@ -60,11 +68,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
> **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
> + qemu_irq irq;
> +
> object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
> ERR_PROP_CHECK_RETURN(err, errp);
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
> qdev_get_gpio_in(DEVICE(&s->cpu[i]),
> ARM_CPU_IRQ));
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
> }
> }
>
> --
> 2.3.1.2.g90df61e.dirty
>
>
- [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names, (continued)
- [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 11/16] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 16/16] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/03/23
- Re: [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC,
Alistair Francis <=
- Re: [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC, Alistair Francis, 2015/03/29