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Re: [Qemu-devel] [RFC 1/5] memory: Define API for MemoryRegionOps to tak
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [RFC 1/5] memory: Define API for MemoryRegionOps to take attrs and return status |
Date: |
Fri, 27 Mar 2015 23:35:22 +1000 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Fri, Mar 27, 2015 at 02:16:53PM +0100, Paolo Bonzini wrote:
>
>
> On 27/03/2015 13:32, Edgar E. Iglesias wrote:
> >>> Is this related to masters relying on the memory frameworks magic
> >>> handling of unaliged accesses?
> >>
> >> Not necessarily, you can get the same just by doing a large write that
> >> spans multiple MemoryRegions. See the loop in address_space_rw.
> >
> > Right, this is another case of "magic" memory handling that allows masters
> > to issue unnatural transactions and rely on the memory framework to
> > split things up.
> > In these cases aren't the masters trading accuracy (including error
> > handling accuracy) for performance or model simplicity?
>
> Yes. There are no "natural" transactions beyond 32 or 64-bit accesses.
>
> > It could maybe be useful to have a flag so masters can say one of the
> > following (could be encoded in the memattrs):
> > 1. Stop at first error and return.
> > 2. Keep going after errors and give me the OR result of all errors.
>
> It could just be a length pointer in the same vein as
> address_space_map's. If NULL, keep going. If not NULL, stop and return.
>
Good point, thanks.
Cheers,
Edgar
[Qemu-devel] [RFC 2/5] memory: Add MemTxAttrs argument to io_mem_read and io_mem_write, Peter Maydell, 2015/03/16
[Qemu-devel] [RFC 4/5] Add MemTxAttrs to the IOTLB, Peter Maydell, 2015/03/16
[Qemu-devel] [RFC 3/5] Make CPU iotlb a structure rather than a plain hwaddr, Peter Maydell, 2015/03/16
[Qemu-devel] [RFC 5/5] target-arm: Honour NS bits in page tables, Peter Maydell, 2015/03/16
Re: [Qemu-devel] [RFC 0/5] Memory transaction attributes API, Edgar E. Iglesias, 2015/03/18