[Qemu-devel] [PATCH 0/6] TriCore: add RRR1, RRRR, RRRW, SYS instructions

[Bastian Koppelmann]

Hi, 

this should be the last major bit of the TriCore integer instructions. The 
floating point ones are a whole
different story. These patches depend on my other TriCore patches 
(https://patchwork.ozlabs.org/patch/438866/)
and add the promised mac instructions for subtract. 
Note here that msub.q behaves a bit strange, e.g. a - (((b * c) << n) >> size), 
with size = size of b and c. 
So the result is only using the upper half of (a * b) << n. However if the 
lower half contains a result > 0 this 
is rounded up to 1 and added to the upper half, since everything is in q31 
format. 

Also this patchset adds the remaining instructions of the RRRR, RRRW and SYS 
format. Note here that I only implemented
non trap instructions, since I'm planing to do trap handling in another patch.

Cheers,
Bastian

Bastian Koppelmann (6):
  target-tricore: Add instructions of RRR1 opcode format, which have
    0xa3 as first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have
    0x63 as first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have
    0xe3 as first opcode
  target-tricore: Add instructions of RRRR opcode format
  target-tricore: Add instructions of RRRW opcode format
  target-tricore: Add instructions of SYS opcode format

 target-tricore/cpu.h             |    7 +
 target-tricore/helper.h          |   12 +
 target-tricore/op_helper.c       |  436 +++
 target-tricore/translate.c       | 6765 +++++++++++++++++++++++---------------
 target-tricore/tricore-opcodes.h |   56 +-
 5 files changed, 4525 insertions(+), 2751 deletions(-)

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2.3.0