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[Qemu-devel] [PATCH] target-arm: always use user mode registers as opera
From: |
Ildar Isaev |
Subject: |
[Qemu-devel] [PATCH] target-arm: always use user mode registers as operands for load/store multiple |
Date: |
Thu, 19 Feb 2015 15:55:36 +0300 |
Pseudocode fragment for STM instruction in ARMv8 spec:
if registers<i> == '1' then // Store User mode register
MemA[address,4] = Rmode[i, M32_User];
Signed-off-by: Ildar Isaev <address@hidden>
---
target-arm/translate.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 622aa03..ca0ce3f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8907,16 +8907,14 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
/* load */
tmp = tcg_temp_new_i32();
gen_aa32_ld32u(tmp, addr, get_mem_index(s));
- if (user) {
+ if (!user && (i == rn)) {
+ loaded_var = tmp;
+ loaded_base = 1;
+ } else {
tmp2 = tcg_const_i32(i);
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp);
- } else if (i == rn) {
- loaded_var = tmp;
- loaded_base = 1;
- } else {
- store_reg_from_load(s, i, tmp);
}
} else {
/* store */
@@ -8925,13 +8923,11 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
val = (long)s->pc + 4;
tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, val);
- } else if (user) {
+ } else {
tmp = tcg_temp_new_i32();
tmp2 = tcg_const_i32(i);
gen_helper_get_user_reg(tmp, cpu_env, tmp2);
tcg_temp_free_i32(tmp2);
- } else {
- tmp = load_reg(s, i);
}
gen_aa32_st32(tmp, addr, get_mem_index(s));
tcg_temp_free_i32(tmp);
--
1.9.3
- [Qemu-devel] [PATCH] target-arm: always use user mode registers as operands for load/store multiple,
Ildar Isaev <=