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Re: [Qemu-devel] [PATCH RFC V2 12/17] hw/pci: introduce PCI Expander Bri
From: |
Alexander Graf |
Subject: |
Re: [Qemu-devel] [PATCH RFC V2 12/17] hw/pci: introduce PCI Expander Bridge (PXB) |
Date: |
Mon, 16 Feb 2015 13:58:39 +0100 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 |
On 16.02.15 10:54, Marcel Apfelbaum wrote:
> From: Marcel Apfelbaum <address@hidden>
>
> PXB is a "light-weight" host bridge whose purpose is to enable
> the main host bridge to support multiple PCI root buses.
>
> As oposed to PCI-2-PCI bridge's secondary bus, PXB's bus
> is a primary bus and can be associated with a NUMA node
> (different from the main host bridge) allowing the guest OS
> to recognize the proximity of a pass-through device to
> other resources as RAM and CPUs.
>
> The PXB is composed from:
> - A primary PCI bus (can be associated with a NUMA node)
> Acts like a normal pci bus and from the functionality point
> of view is an "expansion" of the bus behind the
> main host bridge.
> - A pci-2-pci bridge behind the primary PCI bus where the actual
> devices will be attached.
> - A host-bridge PCI device
> Situated on the bus behind the main host bridge, allows
> the BIOS to configure the bus number and IO/mem resources.
> It does not have its own config/data register for configuration
> cycles, this being handled by the main host bridge.
> - A host-bridge sysbus to comply with QEMU current design.
>
> Signed-off-by: Marcel Apfelbaum <address@hidden>
> ---
> hw/pci-bridge/Makefile.objs | 1 +
> hw/pci-bridge/pci_expander_bridge.c | 173
> ++++++++++++++++++++++++++++++++++++
> include/hw/pci/pci.h | 1 +
> 3 files changed, 175 insertions(+)
> create mode 100644 hw/pci-bridge/pci_expander_bridge.c
>
> diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs
> index 968b369..632e442 100644
> --- a/hw/pci-bridge/Makefile.objs
> +++ b/hw/pci-bridge/Makefile.objs
> @@ -1,4 +1,5 @@
> common-obj-y += pci_bridge_dev.o
> +common-obj-y += pci_expander_bridge.o
> common-obj-y += ioh3420.o xio3130_upstream.o xio3130_downstream.o
> common-obj-y += i82801b11.o
> # NewWorld PowerMac
> diff --git a/hw/pci-bridge/pci_expander_bridge.c
> b/hw/pci-bridge/pci_expander_bridge.c
> new file mode 100644
> index 0000000..941f3c8
> --- /dev/null
> +++ b/hw/pci-bridge/pci_expander_bridge.c
> @@ -0,0 +1,173 @@
> +/*
> + * PCI Expander Bridge Device Emulation
> + *
> + * Copyright (C) 2014 Red Hat Inc
> + *
> + * Authors:
> + * Marcel Apfelbaum <address@hidden>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "hw/pci/pci.h"
> +#include "hw/pci/pci_bus.h"
> +#include "hw/pci/pci_host.h"
> +#include "hw/pci/pci_bus.h"
> +#include "qemu/range.h"
> +#include "qemu/error-report.h"
> +
> +#define TYPE_PXB_BUS "pxb-bus"
> +#define PXB_BUS(obj) OBJECT_CHECK(PXBBus, (obj), TYPE_PXB_BUS)
> +
> +typedef struct PXBBus {
> + /*< private >*/
> + PCIBus parent_obj;
> + /*< public >*/
> +
> + char bus_path[8];
> +} PXBBus;
> +
> +#define TYPE_PXB_DEVICE "pxb-device"
> +#define PXB_DEV(obj) OBJECT_CHECK(PXBDev, (obj), TYPE_PXB_DEVICE)
> +
> +typedef struct PXBDev {
> + /*< private >*/
> + PCIDevice parent_obj;
> + /*< public >*/
> +
> + uint8_t bus_nr;
> +} PXBDev;
> +
> +#define TYPE_PXB_HOST "pxb-host"
> +
> +static int pxb_bus_num(PCIBus *bus)
> +{
> + PXBDev *pxb = PXB_DEV(bus->parent_dev);
> +
> + return pxb->bus_nr;
> +}
> +
> +static bool pxb_is_root(PCIBus *bus)
> +{
> + return true; /* by definition */
> +}
> +
> +static void pxb_bus_class_init(ObjectClass *class, void *data)
> +{
> + PCIBusClass *pbc = PCI_BUS_CLASS(class);
> +
> + pbc->bus_num = pxb_bus_num;
> + pbc->is_root = pxb_is_root;
> +}
> +
> +static const TypeInfo pxb_bus_info = {
> + .name = TYPE_PXB_BUS,
> + .parent = TYPE_PCI_BUS,
> + .instance_size = sizeof(PXBBus),
> + .class_init = pxb_bus_class_init,
> +};
> +
> +static const char *pxb_host_root_bus_path(PCIHostState *host_bridge,
> + PCIBus *rootbus)
> +{
> + PXBBus *bus = PXB_BUS(rootbus);
> +
> + snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus));
> + return bus->bus_path;
> +}
> +
> +static void pxb_host_class_init(ObjectClass *class, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(class);
> + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
> +
> + dc->fw_name = "pci";
> + hc->root_bus_path = pxb_host_root_bus_path;
> +}
> +
> +static const TypeInfo pxb_host_info = {
> + .name = TYPE_PXB_HOST,
> + .parent = TYPE_PCI_HOST_BRIDGE,
> + .class_init = pxb_host_class_init,
> +};
> +
> +static int pxb_dev_initfn(PCIDevice *dev)
> +{
> + PXBDev *pxb = PXB_DEV(dev);
> + DeviceState *ds, *bds;
> + PCIHostState *phs;
> + PCIBus *bus;
> + const char *dev_name = NULL;
> +
> + HOST_BRIDGE_FOREACH(phs) {
> + if (pxb->bus_nr == pci_bus_num(phs->bus)) {
> + error_report("Bus nr %d is already used by %s.",
> + pxb->bus_nr, phs->bus->qbus.name);
> + return -EINVAL;
> + }
> + }
> +
> + if (dev->qdev.id && *dev->qdev.id) {
> + dev_name = dev->qdev.id;
> + }
> +
> + ds = qdev_create(NULL, TYPE_PXB_HOST);
> + bus = pci_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
> +
> + bus->parent_dev = dev;
> + bus->address_space_mem = dev->bus->address_space_mem;
> + bus->address_space_io = dev->bus->address_space_io;
> + bus->map_irq = pci_swizzle_map_irq_fn;
> +
> + bds = qdev_create(BUS(bus), "pci-bridge");
> + bds->id = dev_name;
> + qdev_prop_set_uint8(bds, "chassis_nr", pxb->bus_nr);
> +
> + PCI_HOST_BRIDGE(ds)->bus = bus;
> +
> + qdev_init_nofail(ds);
> + qdev_init_nofail(bds);
> +
> + pci_word_test_and_set_mask(dev->config + PCI_STATUS,
> + PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
> + pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
> +
> + return 0;
> +}
> +
> +static Property pxb_dev_properties[] = {
> + /* Note: 0 is not a legal a PXB bus number. */
> + DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pxb_dev_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->init = pxb_dev_initfn;
> + k->vendor_id = PCI_VENDOR_ID_REDHAT;
> + k->device_id = PCI_DEVICE_ID_REDHAT_PXB;
> + k->class_id = PCI_CLASS_BRIDGE_HOST;
> +
> + dc->desc = "PCI Expander Bridge";
> + dc->props = pxb_dev_properties;
> +}
> +
> +static const TypeInfo pxb_dev_info = {
> + .name = TYPE_PXB_DEVICE,
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(PXBDev),
> + .class_init = pxb_dev_class_init,
> +};
> +
> +static void pxb_register_types(void)
> +{
> + type_register_static(&pxb_bus_info);
> + type_register_static(&pxb_host_info);
> + type_register_static(&pxb_dev_info);
> +}
> +
> +type_init(pxb_register_types)
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index b7e24d4..e936528 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -89,6 +89,7 @@
> #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
> #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
> #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
> +#define PCI_DEVICE_ID_REDHAT_PXB 0x0008
This collides with the new PCI root device that should be in the tree by
now :).
Alex
- [Qemu-devel] [PATCH RFC V2 00/17] hw/pc: implement multiple primary busses for pc machines, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 08/17] hw/pci: made pci_bus_num a PCIBusClass method, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 06/17] hw/pci: move pci bus related code to separate files, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 11/17] hw/pci: implement iteration over multiple host bridges, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 12/17] hw/pci: introduce PCI Expander Bridge (PXB), Marcel Apfelbaum, 2015/02/16
- Re: [Qemu-devel] [PATCH RFC V2 12/17] hw/pci: introduce PCI Expander Bridge (PXB),
Alexander Graf <=
- [Qemu-devel] [PATCH RFC V2 07/17] hw/pci: made pci_bus_is_root a PCIBusClass method, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 13/17] hw/pci: inform bios if the system has more than one pci bridge, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 09/17] hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 05/17] hw/acpi: remove from root bus 0 the crs resources used by other busses., Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 15/17] hw/pxb: add map_irq func, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 16/17] hw/pci_bus: add support for NUMA nodes, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 10/17] hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 03/17] hw/apci: add _PRT method for extra root busses, Marcel Apfelbaum, 2015/02/16
- [Qemu-devel] [PATCH RFC V2 01/17] acpi: added needed acpi constructs, Marcel Apfelbaum, 2015/02/16