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[Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled |
Date: |
Thu, 5 Feb 2015 14:02:47 +0000 |
Add assertion checking when cpreg structures are registered that they
either forbid raw-access attempts or at least make an attempt at
handling them. Also add an assert in the raw-accessor-of-last-resort,
to avoid silently doing a read or write from offset zero, which is
actually AArch32 CPU register r0.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d214c9a..3b054ad 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -119,6 +119,7 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env,
uint8_t *buf, int reg)
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
+ assert(ri->fieldoffset);
if (cpreg_field_is_64bit(ri)) {
return CPREG_FIELD64(env, ri);
} else {
@@ -129,6 +130,7 @@ static uint64_t raw_read(CPUARMState *env, const
ARMCPRegInfo *ri)
static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ assert(ri->fieldoffset);
if (cpreg_field_is_64bit(ri)) {
CPREG_FIELD64(env, ri) = value;
} else {
@@ -174,6 +176,27 @@ static void write_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
+static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
+{
+ /* Return true if the regdef would cause an assertion if you called
+ * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
+ * program bug for it not to have the NO_RAW flag).
+ * NB that returning false here doesn't necessarily mean that calling
+ * read/write_raw_cp_reg() is safe, because we can't distinguish "has
+ * read/write access functions which are safe for raw use" from "has
+ * read/write access functions which have side effects but has forgotten
+ * to provide raw access functions".
+ * The tests here line up with the conditions in read/write_raw_cp_reg()
+ * and assertions in raw_read()/raw_write().
+ */
+ if ((ri->type & ARM_CP_CONST) ||
+ ri->fieldoffset ||
+ ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
+ return false;
+ }
+ return true;
+}
+
bool write_cpustate_to_list(ARMCPU *cpu)
{
/* Write the coprocessor state from cpu->env to the (index,value) list. */
@@ -3536,6 +3559,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
r2->type |= ARM_CP_ALIAS;
}
+ /* Check that raw accesses are either forbidden or handled. Note that
+ * we can't assert this earlier because the setup of fieldoffset for
+ * banked registers has to be done first.
+ */
+ if (!(r2->type & ARM_CP_NO_RAW)) {
+ assert(!raw_accessors_invalid(r2));
+ }
+
/* Overriding of an existing definition must be explicitly
* requested.
*/
--
1.9.1
- [Qemu-devel] [PULL 28/28] target-arm: fix for exponent comparison in recpe_f64, (continued)
- [Qemu-devel] [PULL 28/28] target-arm: fix for exponent comparison in recpe_f64, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 26/28] target-arm: KVM64: Get and Sync up guest register state like kvm32., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 27/28] target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 25/28] disas/arm-a64.cc: Tell libvixl correct code addresses, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 23/28] target-arm: Fix brace style in reindented code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 12/28] hw/arm/virt: explain device-to-transport mapping in create_virtio_devices(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled,
Peter Maydell <=
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05