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[Qemu-devel] [PULL 00/13] tricore patches
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 00/13] tricore patches |
Date: |
Sun, 21 Dec 2014 18:47:36 +0000 |
The following changes since commit c4e7c17a8ecb41cdbb81374a128161c614ba1f1e:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-20141217-1' into
staging (2014-12-20 21:28:53 +0000)
are available in the git repository at:
https://github.com/bkoppelmann/qemu-tricore-upstream.git
tags/pull-tricore-20141221
for you to fetch changes up to 9655b9328a566116c198c52792775a0641d56915:
target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as
first opcode (2014-12-21 18:35:49 +0000)
----------------------------------------------------------------
TriCore RR, RR1 insn added and several bug fixes
----------------------------------------------------------------
Alex Zuepke (4):
target-tricore: fix offset masking in BOL format
target-tricore: typo in BOL format
target-tricore: add missing 64-bit MOV in RLC format
target-tricore: pretty-print register dump and show more status registers
Bastian Koppelmann (9):
target-tricore: Fix mask handling JNZ.T being 7 bit long
target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
target-tricore: Add instructions of RR opcode format, that have 0xb as
the first opcode
target-tricore: Add instructions of RR opcode format, that have 0xf as
the first opcode
target-tricore: Add instructions of RR opcode format, that have 0x1 as
the first opcode
target-tricore: Add instructions of RR opcode format, that have 0x4b as
the first opcode
target-tricore: Add missing 1.6 insn of BOL opcode format
target-tricore: Fix MFCR/MTCR insn and B format offset.
target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as
first opcode
target-tricore/helper.h | 59 +++
target-tricore/op_helper.c | 1086 +++++++++++++++++++++++++++++++++++---
target-tricore/translate.c | 1034 +++++++++++++++++++++++++++++++++++-
target-tricore/tricore-opcodes.h | 19 +-
4 files changed, 2104 insertions(+), 94 deletions(-)
--
2.2.1
- [Qemu-devel] [PULL 00/13] tricore patches,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format, Bastian Koppelmann, 2014/12/21