[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B for
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset. |
Date: |
Wed, 17 Dec 2014 15:59:20 +0000 |
Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 6 ++++--
target-tricore/tricore-opcodes.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5691267..8940a23 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3930,6 +3930,7 @@ static void decode_rlc_opc(CPUTriCoreState *env,
DisasContext *ctx,
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
break;
case OPC1_32_RLC_MFCR:
+ const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mfcr(env, cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV:
@@ -3946,7 +3947,8 @@ static void decode_rlc_opc(CPUTriCoreState *env,
DisasContext *ctx,
tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
break;
case OPC1_32_RLC_MTCR:
- gen_mtcr(env, ctx, cpu_gpr_d[r2], const16);
+ const16 = MASK_OP_RLC_CONST16(ctx->opcode);
+ gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
break;
}
}
@@ -4650,7 +4652,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
case OPC1_32_B_JA:
case OPC1_32_B_JL:
case OPC1_32_B_JLA:
- address = MASK_OP_B_DISP24(ctx->opcode);
+ address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
/* Bit-format */
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 5274765..1273f3d 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -94,6 +94,8 @@
/* B Format */
#define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
(MASK_BITS_SHIFT(op, 8, 15) << 16))
+#define MASK_OP_B_DISP24_SEXT(op) (MASK_BITS_SHIFT(op, 16, 31) + \
+ (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16))
/* BIT Format */
#define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
#define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
--
2.1.3
- [Qemu-devel] [PATCH v2 0/8] TriCore add instructions of RR and RR1 opcode format, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset.,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v2 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH v2 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Bastian Koppelmann, 2014/12/17