Re: [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode

[Peter Maydell]

On 3 December 2014 at 20:53, Chengyu Song <address@hidden> wrote:
> The version I use is A.a Non-Confidential Beta, release on 04 September
> 2013. I don't have any later version.

We're up to rev A.d now; you can get it from
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487a.d/index.html
(if you haven't registered on the ARM website before you'll need
to fill in a form but it's a fairly painless process.)

>>> +      .opc0 = 3, .crn = 9, .crm = 12, .opc1 = 3, .opc2 = 3,
>>
>> It might be helpful to order the fields opc0, opc1, crn, crm, opc2 to match
>> the documentation and some (most?) of the other A64 QEMU code.
>
> Good point. Let me try to resubmit the patch.

The order we're preferring is the v8 ARM ARM order, so
that's .opc0, .opc1, .crn, .crm, .opc2. (Some of our existing
code doesn't follow that, unfortunately.)

>> Should PMOVSSET_EL0 also be added?
>
> PMOVSSET is not available in QEMU, so I'm not sure how it should be added

By implementing the register's behaviour; there's only one
bit of state we care about since we don't model any
perf counters except the cycle counter. The overflow bit
is handled by a set/clear pair of register accessors,
and we also need to check on reads to see if the
cycle counter would have overflowed (in which case we
need to set the bit to 1), using a similar logic to how
we deal with reads of the cycle counter itself. (A similar
check also needs to be done when the cycle counter is
written to or when it is disabled.)

Are there any other bits of new-in-v8 perf counter
functionality we're missing?

thanks
-- PMM