[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write acc
|
From: |
Leon Alrae |
|
Subject: |
Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses |
|
Date: |
Tue, 2 Dec 2014 10:52:27 +0000 |
|
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 18/11/2014 03:59, Maciej W. Rozycki wrote:
> Please note that for this validation I'm using an artificial microMIPS
> processor that also has an FPU implemented, so that our microMIPS FP
> support is correctly validated too (I don't really know if there exists
> any real microMIPS processor that includes an FPU; if so, then it would
> be good to add it to the list our supported configurations).
FYI, there are real CPUs which support microMIPS and include FPU, for
example microAptivUC.
> qemu-mips-config3-isaonexc.diff
Reviewed-by: Leon Alrae <address@hidden>
- Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses,
Leon Alrae <=