Re: [Qemu-devel] [PATCH v3 4/4] target-tricore: Add instructions of RCR opcode format

[Richard Henderson]

On 11/20/2014 02:28 PM, Bastian Koppelmann wrote:
> +uint64_t helper_madd64_ssov(CPUTriCoreState *env, target_ulong r1,
> +                            uint64_t r2, target_ulong r3)
> +{
> +    uint64_t ret_low, ret_high;
> +    uint64_t r2_high;
> +    int64_t t1 = sextract64(r1, 0, 32);
> +    int64_t t3 = sextract64(r3, 0, 32);
> +
> +    ret_low = t1 * t3;
> +    ret_high = ((int64_t)ret_low >> 63);
> +    r2_high = ((int64_t)r2 >> 63);
> +    add128(&ret_low, &ret_high, r2, r2_high);
> +
> +    /* check for saturate */
> +    t1 = (int64_t)ret_low >> 63;
> +    if (t1 != ret_high) {

Instead of 128-bit addition, just use the "normal" overflow detection:

  mul = t1 * t3;
  ret = mul + r2;
  ovf = (ret ^ mul) & ~(mul ^ r2);
  if ((int64_t)ovf < 0)


> +uint64_t helper_madd64_suov(CPUTriCoreState *env, target_ulong r1,
> +                            uint64_t r2, target_ulong r3)
> +{
> +    uint64_t ret_low, ret_high;
> +    uint64_t t1 = extract64(r1, 0, 32);
> +    uint64_t t3 = extract64(r3, 0, 32);
> +
> +    ret_low = t1 * t3;
> +    ret_high = 0;
> +    add128(&ret_low, &ret_high, r2, 0);
> +
> +    if (ret_high != 0) {

I'm sure this is similar, though easier since its unsigned:

  mul = t1 * t3;
  ret = mul + r2;
  if (ret < r2)

> +        env->PSW_USB_V = (1 << 31);
> +        env->PSW_USB_SV = (1 << 31);
> +        ret_low = UINT64_MAX;
> +    } else if ((ret_high & (1LL << 63)) != 0) {

I'm not sure what this is about though, since your "ret_high != 0" shadows it,
so it'll never be executed.  Cut and paste from ssov, or is the addition
actually signed?

> +uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
> +                            uint64_t r2, target_ulong r3)
...
> +uint64_t helper_msub64_suov(CPUTriCoreState *env, target_ulong r1,
> +                            uint64_t r2, target_ulong r3)

Likewise, of course.

Otherwise, it looks good.


r~