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[Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQ
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ |
Date: |
Fri, 7 Nov 2014 16:56:07 +0000 |
New R6 COP1 conditional branches currently don't have delay slot. Fixing this
by setting MIPS_HFLAG_BDS32 flag which is required for branches having 4-byte
delay slot.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d6722e1..194d4fb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8104,6 +8104,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,
uint32_t op,
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
out:
tcg_temp_free_i64(t0);
--
2.1.0
- [Qemu-devel] [PULL 0/7] target-mips queue, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 1/7] mips: Remove CONFIG_VT82C686 from non-Fulong configs, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ,
Leon Alrae <=
- Re: [Qemu-devel] [PULL 0/7] target-mips queue, Peter Maydell, 2014/11/10