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Re: [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstr
From: |
Leon Alrae |
Subject: |
Re: [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support |
Date: |
Sat, 1 Nov 2014 19:27:28 +0000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 |
Hi Yongbok,
On 29/10/14 13:55, Yongbok Kim wrote:
> On 24/10/2014 13:42, Leon Alrae wrote:
>> case EXCP_TLBRI:
>> cause = 19;
>> + update_badinstr = 1;
>> goto set_EPC;
>> case EXCP_TLBXI:
>> cause = 20;
>
> TLBXI requires updating the register.
TLBXI exception can be generated by instruction fetch or MIPS16
PC-relative load. IIUC if TLBXI is caused by instruction fetch the value
stored in BadInstr is unpredictable as valid instruction word is not
available (the same case as TLB Refill - Instruction Fetch). Therefore
in context of Release 6 the implementation is correct. As far as MIPS16
is concerned, this is similar limitation which we discussed for patch #4
(i.e. MIPS16 PC-relative load should ignore RI bit).
Regards,
Leon
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Leon Alrae <=