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[Qemu-devel] [PATCH v8 00/27] target-arm: add Security Extensions for CP
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v8 00/27] target-arm: add Security Extensions for CPUs |
Date: |
Thu, 30 Oct 2014 16:28:31 -0500 |
Version 8 of the ARM processor security extension (TrustZone) support. This
patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Patches 1-6 of version 7 have already been accepted and committed.
Summary of changes from v7 -> v8:
- Reworked exception maskign and target EL functions to use table lookups
instead of extensive conditionals.
- Moved and renamed use_secure_reg to access_secure_reg
- Redo fieldoffset definitions to eliminate #defines
- Consolidated common secure v7/v8 CP regs
- Removed NSACR read/write functions
- Fixed SDER and added SDER32_EL3
- Made MVBAR a 32-bit field
- Fixed CPSR write logic
- Fixed various code and commit comments
- Fixed CSSELR CP definition to use OPC0
Fabian Aggeler (20):
target-arm: add banked register accessors
target-arm: add CPREG secure state support
target-arm: insert AArch32 cpregs twice into hashtable
target-arm: move AArch32 SCR into security reglist
target-arm: implement IRQ/FIQ routing to Monitor mode
target-arm: add NSACR register
target-arm: add MVBAR support
target-arm: add SCTLR_EL3 and make SCTLR banked
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
target-arm: make CSSELR banked
target-arm: add TTBR0_EL3 and make TTBR0/1 banked
target-arm: add TCR_EL3 and make TTBCR banked
target-arm: make c2_mask and c2_base_mask banked
target-arm: make DACR banked
target-arm: make IFSR banked
target-arm: make DFSR banked
target-arm: make IFAR/DFAR banked
target-arm: make PAR banked
target-arm: make c13 cp regs banked (FCSEIDR, ...)
target-arm: add cpu feature EL3 to CPUs with Security Extensions
Greg Bellows (5):
target-arm: extend async excp masking
target-arm: add async excp target_el function
target-arm: add secure state bit to CPREG hash
target-arm: make VBAR banked
target-arm: make MAIR0/1 banked
Sergey Fedorov (2):
target-arm: add non-secure Translation Block flag
target-arm: add SDER definition
hw/arm/pxa2xx.c | 8 +-
linux-user/aarch64/target_cpu.h | 2 +-
linux-user/arm/target_cpu.h | 2 +-
linux-user/main.c | 72 ++---
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 525 ++++++++++++++++++++++++++++----
target-arm/helper.c | 655 +++++++++++++++++++++++++++++-----------
target-arm/internals.h | 2 +-
target-arm/op_helper.c | 4 +-
target-arm/translate.c | 17 +-
target-arm/translate.h | 1 +
11 files changed, 1015 insertions(+), 284 deletions(-)
--
1.8.3.2
- [Qemu-devel] [PATCH v8 00/27] target-arm: add Security Extensions for CPUs,
Greg Bellows <=
- [Qemu-devel] [PATCH v8 22/27] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 19/27] target-arm: make DACR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 18/27] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 16/27] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 21/27] target-arm: make DFSR banked, Greg Bellows, 2014/10/31