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Re: [Qemu-devel] Better Cortex-M support?
From: |
Liviu Ionescu |
Subject: |
Re: [Qemu-devel] Better Cortex-M support? |
Date: |
Tue, 28 Oct 2014 15:23:37 +0200 |
On 28 Oct 2014, at 14:57, Peter Maydell <address@hidden> wrote:
> On 28 October 2014 12:52, Liviu Ionescu <address@hidden> wrote:
>>
>> On 28 Oct 2014, at 14:45, Peter Maydell <address@hidden> wrote:
>>
>>>> qemu: Unsupported SemiHosting SWI 0x00
>>>> R00=00000000 R01=00000000 R02=00000000 R03=00000000
>>>> R04=00000000 R05=00000000 R06=00000000 R07=200ffed8
>>>> R08=00000000 R09=00000000 R10=00000000 R11=00000000
>>>> R12=00000000 R13=200ffed8 R14=000022c5 R15=0000157c
>>>> PSR=60000173 -ZC- T svc32
>>>> Abort trap: 6
>>>
>>> What code sequence and which semihosting function are
>>> you trying to use here?
>>
> ...
> Can you give the disassembly of the actual code making
> the semihosting request, please? As you can see we seem
> to have interpreted this as a semihosting function zero,
> not 4, but it's hard to see why without seeing what the
> assembly instructions are that your code is executing.
right, I did some more tests, and the the actual code is:
00001564 <_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>:
{
// ======================================================================
int
SemiHosting::BKPT(int op, void* p1, void* p2)
{
1564: b480 push {r7}
1566: b085 sub sp, #20
1568: af00 add r7, sp, #0
156a: 60f8 str r0, [r7, #12]
156c: 60b9 str r1, [r7, #8]
156e: 607a str r2, [r7, #4]
register int r0 asm("r0");
register int r1 asm("r1") __attribute__((unused));
register int r2 asm("r2") __attribute__((unused));
r0 = op;
1570: 68f8 ldr r0, [r7, #12]
r1 = (int) p1;
1572: 68bb ldr r3, [r7, #8]
1574: 4619 mov r1, r3
r2 = (int) p2;
1576: 687b ldr r3, [r7, #4]
1578: 461a mov r2, r3
asm volatile(""
" bkpt 0xAB \n"
: "=r"(r0)
:
:
);
157a: beab bkpt 0x00ab
return r0;
157c: 4603 mov r3, r0
}
157e: 4618 mov r0, r3
1580: 3714 adds r7, #20
1582: 46bd mov sp, r7
1584: f85d 7b04 ldr.w r7, [sp], #4
1588: 4770 bx lr
158a: bf00 nop
I also collected all calls in the test:
BKPT(0x04, (void*) pString, (void*) 0);
270: 2004 movs r0, #4
272: 68f9 ldr r1, [r7, #12]
274: 2200 movs r2, #0
276: f001 f975 bl 1564
<_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>
// ADP_Stopped_ApplicationExit
// (qemu ignores this value)
BKPT(0x18, (void*) 0x20026, (void*) 0);
227a: 2018 movs r0, #24
227c: 4906 ldr r1, [pc, #24] ; (2298
<_ZN3hal4qemu4diag11SemiHosting4exitEi+0x2c>)
227e: 2200 movs r2, #0
2280: f7ff f970 bl 1564
<_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>
2284: e006 b.n 2294
<_ZN3hal4qemu4diag11SemiHosting4exitEi+0x28>
// Generate an unsupported call, to force qemu to quit.
BKPT(0xF0 + code, (void*) 0, (void*) 0);
2286: 687b ldr r3, [r7, #4]
2288: 33f0 adds r3, #240 ; 0xf0
228a: 4618 mov r0, r3
228c: 2100 movs r1, #0
228e: 2200 movs r2, #0
2290: f7ff f968 bl 1564
<_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>
22b6: 697b ldr r3, [r7, #20]
22b8: 60fb str r3, [r7, #12]
22ba: 2004 movs r0, #4
22bc: 68f9 ldr r1, [r7, #12]
22be: 2200 movs r2, #0
22c0: f7ff f950 bl 1564
<_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>
BKPT(0x03, (void*) &ch, (void*) 0);
22d2: f107 030b add.w r3, r7, #11
22d6: 2003 movs r0, #3
22d8: 4619 mov r1, r3
22da: 2200 movs r2, #0
22dc: f7ff f942 bl 1564
<_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>
none seem to pass a zero value in R0.
I would check the way "bkpt 0x00ab" is processed.
you can also check the differences from Bechus version.
regards,
Liviu
- [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?,
Liviu Ionescu <=
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Liviu Ionescu, 2014/10/28
- Re: [Qemu-devel] Better Cortex-M support?, Peter Maydell, 2014/10/28