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[Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard aroun
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64() |
Date: |
Wed, 15 Oct 2014 10:54:18 +0100 |
From: Peter Maydell <address@hidden>
The function check_mips64() is only used if TARGET_MIPS64 is defined;
add an ifdef guard to its definition to avoid warnings about it being
unused in other configurations.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8b62e66..c23cb94 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1548,6 +1548,7 @@ static inline void check_insn_opc_removed(DisasContext
*ctx, int flags)
}
}
+#ifdef TARGET_MIPS64
/* This code generates a "reserved instruction" exception if 64-bit
instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx)
@@ -1555,6 +1556,7 @@ static inline void check_mips_64(DisasContext *ctx)
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
generate_exception(ctx, EXCP_RI);
}
+#endif
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
--
2.1.0
- [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches, (continued)
- [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 18/28] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 17/28] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64(),
Leon Alrae <=
- [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX, Leon Alrae, 2014/10/15
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/16
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/22