Re: [Qemu-devel] [PATCH v3 03/21] target-mips: add SELEQZ and SELNEZ instructions

[James Hogan]

On 26/09/14 13:45, Leon Alrae wrote:
> Hi James,
> 
> On 26/09/2014 13:03, James Hogan wrote:
>> Hi Leon,
>>
>> On 27/06/14 16:21, Leon Alrae wrote:
>>>  /* MIPS64 MIPS-3D ASE support.  */
>>>  #define I16     INSN_MIPS16
>>> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>>>     them first.  The assemblers uses a hash table based on the
>>>     instruction name anyhow.  */
>>>  /* name,    args,  match,      mask,       pinfo,                  
>>> membership */
>>> +{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, 
>>> I32R6},
>>> +{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, 
>>> I32R6},
>>
>> I don't think these need to be at the beginning of the table since
>> they're normal instructions, unlike "nop" for example which is encoded
>> as a "sll".
> 
> I don't have any preference on this, just wanted to have new R6
> instructions grouped. As I can see in binutils new R6 instructions were
> placed at the bottom so I could stick to it as well.

It just seems like most of them are alphabetical in the main group, the
few at the top before "abs" seem to be specifically aliases of other
instructions, and the other groups at the bottom are there for specific
reasons too by the looks of it.

It's not my code though so if others are fine with it, so be it.

Cheers
James