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[Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ |
Date: |
Fri, 26 Sep 2014 18:08:34 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
This only implements the external delivery method via the GIC.
Acked-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
cpu-exec.c | 12 ++++++++++++
target-arm/cpu.c | 35 ++++++++++++++++++++++++-----------
target-arm/cpu.h | 35 ++++++++++++++++++++++++++++++++---
target-arm/helper-a64.c | 2 ++
target-arm/helper.c | 4 ++++
target-arm/internals.h | 2 ++
6 files changed, 76 insertions(+), 14 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index d017588..6203ba5 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -616,6 +616,18 @@ int cpu_exec(CPUArchState *env)
cc->do_interrupt(cpu);
next_tb = 0;
}
+ if (interrupt_request & CPU_INTERRUPT_VIRQ
+ && arm_excp_unmasked(cpu, EXCP_VIRQ)) {
+ cpu->exception_index = EXCP_VIRQ;
+ cc->do_interrupt(cpu);
+ next_tb = 0;
+ }
+ if (interrupt_request & CPU_INTERRUPT_VFIQ
+ && arm_excp_unmasked(cpu, EXCP_VFIQ)) {
+ cpu->exception_index = EXCP_VFIQ;
+ cc->do_interrupt(cpu);
+ next_tb = 0;
+ }
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7ea12bd..209ad2b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -41,7 +41,9 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
static bool arm_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request &
- (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+ (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
+ | CPU_INTERRUPT_EXITTB);
}
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
@@ -192,21 +194,29 @@ static void arm_cpu_reset(CPUState *s)
static void arm_cpu_set_irq(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
+ CPUARMState *env = &cpu->env;
CPUState *cs = CPU(cpu);
+ static const int mask[] = {
+ [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
+ [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
+ [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
+ [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
+ };
switch (irq) {
- case ARM_CPU_IRQ:
- if (level) {
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- } else {
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ case ARM_CPU_VIRQ:
+ case ARM_CPU_VFIQ:
+ if (!arm_feature(env, ARM_FEATURE_EL2)) {
+ hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
+ __func__, irq);
}
- break;
+ /* fall through */
+ case ARM_CPU_IRQ:
case ARM_CPU_FIQ:
if (level) {
- cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
+ cpu_interrupt(cs, mask[irq]);
} else {
- cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
+ cpu_reset_interrupt(cs, mask[irq]);
}
break;
default:
@@ -256,9 +266,12 @@ static void arm_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
/* Our inbound IRQ and FIQ lines */
if (kvm_enabled()) {
- qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
+ /* VIRQ and VFIQ are unused with KVM but we add them to maintain
+ * the same interface as non-KVM CPUs.
+ */
+ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
} else {
- qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
+ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
}
cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 00b3ad4..aa6fb3c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -54,6 +54,8 @@
#define EXCP_HVC 11 /* HyperVisor Call */
#define EXCP_HYP_TRAP 12
#define EXCP_SMC 13 /* Secure Monitor Call */
+#define EXCP_VIRQ 14
+#define EXCP_VFIQ 15
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
@@ -68,6 +70,8 @@
/* ARM-specific interrupt pending bits. */
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
+#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
/* The usual mapping for an AArch64 system register to its AArch32
* counterpart is for the 32 bit world to have access to the lower
@@ -83,9 +87,11 @@
#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
#endif
-/* Meanings of the ARMCPU object's two inbound GPIO lines */
+/* Meanings of the ARMCPU object's four inbound GPIO lines */
#define ARM_CPU_IRQ 0
#define ARM_CPU_FIQ 1
+#define ARM_CPU_VIRQ 2
+#define ARM_CPU_VFIQ 3
typedef void ARMWriteCPFunc(void *opaque, int cp_info,
int srcreg, int operand, uint32_t value);
@@ -1183,6 +1189,18 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
bool secure = false;
/* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */
bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
+ /* ARMv7-M interrupt return works by loading a magic value
+ * into the PC. On real hardware the load causes the
+ * return to occur. The qemu implementation performs the
+ * jump normally, then does the exception return when the
+ * CPU tries to execute code at the magic address.
+ * This will cause the magic PC value to be pushed to
+ * the stack if an interrupt occurred at the wrong time.
+ * We avoid this by disabling interrupts when
+ * pc contains a magic address.
+ */
+ bool irq_unmasked = !(env->daif & PSTATE_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0);
/* Don't take exceptions if they target a lower EL. */
if (cur_el > target_el) {
@@ -1199,8 +1217,19 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
return true;
}
- return !(env->daif & PSTATE_I)
- && (!IS_M(env) || env->regs[15] < 0xfffffff0);
+ return irq_unmasked;
+ case EXCP_VFIQ:
+ if (!secure && !(env->cp15.hcr_el2 & HCR_FMO)) {
+ /* VFIQs are only taken when hypervized and non-secure. */
+ return false;
+ }
+ return !(env->daif & PSTATE_F);
+ case EXCP_VIRQ:
+ if (!secure && !(env->cp15.hcr_el2 & HCR_IMO)) {
+ /* VIRQs are only taken when hypervized and non-secure. */
+ return false;
+ }
+ return irq_unmasked;
default:
g_assert_not_reached();
}
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 0011488..8228e29 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -482,9 +482,11 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
case EXCP_IRQ:
+ case EXCP_VIRQ:
addr += 0x80;
break;
case EXCP_FIQ:
+ case EXCP_VFIQ:
addr += 0x100;
break;
default:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c3a70d6..098a507 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3687,6 +3687,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
}
break;
}
+ case EXCP_VIRQ:
+ case EXCP_VFIQ:
+ target_el = 1;
+ break;
default:
target_el = MAX(cur_el, 1);
break;
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 198cc0e..9bb40ca 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -56,6 +56,8 @@ static const char * const excnames[] = {
[EXCP_HVC] = "Hypervisor Call",
[EXCP_HYP_TRAP] = "Hypervisor Trap",
[EXCP_SMC] = "Secure Monitor Call",
+ [EXCP_VIRQ] = "Virtual IRQ",
+ [EXCP_VFIQ] = "Virtual FIQ",
};
static inline void arm_log_exception(int idx)
--
1.9.1
- [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2, (continued)
- [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 05/11] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 06/11] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 07/11] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v7 03/11] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 09/11] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/26
- Re: [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model, Peter Maydell, 2014/09/26