[Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

This patch series enable floating point instruction in 440x5 CPUs
which have the capabilities to have optional APU FPU in double precision mode.

1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
2) Create a new 440x5 implementing floating point instructions

Pierre Mallard (2):
  target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64
  target-ppc : Add new processor type 440x5wDFPU

 target-ppc/cpu-models.c     |    3 +++
 target-ppc/cpu.h            |    5 ++++-
 target-ppc/fpu_helper.c     |    6 ------
 target-ppc/helper.h         |    4 +---
 target-ppc/translate.c      |   18 +++++++----------
 target-ppc/translate_init.c |   47 ++++++++++++++++++++++++++++++++++++++++---
 6 files changed, 59 insertions(+), 24 deletions(-)

-- 
1.7.10.4