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Re: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Update OPC_SYNCI
From: |
Yongbok Kim |
Subject: |
Re: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Update OPC_SYNCI |
Date: |
Wed, 10 Sep 2014 15:12:23 +0000 |
Reviewed-by: Yongbok Kim <address@hidden>
Note that there is a microMIPS version of SYNCI, it would be even better if you
could update it as well.
Best Regards,
Yongbok Kim
-----Original Message-----
From: address@hidden [mailto:address@hidden On Behalf Of Dongxue Zhang
Sent: Tuesday, July 29, 2014 2:48 PM
To: address@hidden
Cc: address@hidden; Dongxue Zhang; address@hidden
Subject: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Update OPC_SYNCI
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang <address@hidden>
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c381366..dc8afcf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15334,7 +15334,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
- /* Treat as NOP. */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
--
1.8.1.2
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