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[Qemu-devel] [PULL v2 01/16] iommu: add is_write as a parameter to the t
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 01/16] iommu: add is_write as a parameter to the translate function of MemoryRegionIOMMUOps |
Date: |
Wed, 3 Sep 2014 16:44:48 +0300 |
From: Le Tan <address@hidden>
Add a bool variable is_write as a parameter to the translate function of
MemoryRegionIOMMUOps to indicate the operation of the access. It can be
used for correct fault reporting from within the callback.
Change the interface of related functions.
Signed-off-by: Le Tan <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
include/exec/memory.h | 2 +-
exec.c | 2 +-
hw/alpha/typhoon.c | 3 ++-
hw/pci-host/apb.c | 3 ++-
hw/ppc/spapr_iommu.c | 3 ++-
5 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index d165b27..ea381d6 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -129,7 +129,7 @@ typedef struct MemoryRegionIOMMUOps MemoryRegionIOMMUOps;
struct MemoryRegionIOMMUOps {
/* Return a TLB entry that contains a given address. */
- IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr);
+ IOMMUTLBEntry (*translate)(MemoryRegion *iommu, hwaddr addr, bool
is_write);
};
typedef struct CoalescedMemoryRange CoalescedMemoryRange;
diff --git a/exec.c b/exec.c
index 5f9857c..5122a33 100644
--- a/exec.c
+++ b/exec.c
@@ -373,7 +373,7 @@ MemoryRegion *address_space_translate(AddressSpace *as,
hwaddr addr,
break;
}
- iotlb = mr->iommu_ops->translate(mr, addr);
+ iotlb = mr->iommu_ops->translate(mr, addr, is_write);
addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
| (addr & iotlb.addr_mask));
len = MIN(len, (addr | iotlb.addr_mask) - addr + 1);
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 67a1070..31947d9 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -660,7 +660,8 @@ static bool window_translate(TyphoonWindow *win, hwaddr
addr,
/* Handle PCI-to-system address translation. */
/* TODO: A translation failure here ought to set PCI error codes on the
Pchip and generate a machine check interrupt. */
-static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr addr)
+static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr addr,
+ bool is_write)
{
TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu);
IOMMUTLBEntry ret;
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 60bd81e..762ebdd 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -204,7 +204,8 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void
*opaque, int devfn)
return &is->iommu_as;
}
-static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr)
+static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr,
+ bool is_write)
{
IOMMUState *is = container_of(iommu, IOMMUState, iommu);
hwaddr baseaddr, offset;
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index f6e32a4..6c91d8e 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -59,7 +59,8 @@ static sPAPRTCETable *spapr_tce_find_by_liobn(uint32_t liobn)
return NULL;
}
-static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr
addr)
+static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr
addr,
+ bool is_write)
{
sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
uint64_t tce;
--
MST
- [Qemu-devel] [PULL v2 00/16] pci, pc fixes, features, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 02/16] intel-iommu: introduce Intel IOMMU (VT-d) emulation, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 03/16] intel-iommu: add DMAR table to ACPI tables, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 01/16] iommu: add is_write as a parameter to the translate function of MemoryRegionIOMMUOps,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 06/16] intel-iommu: add supports for queued invalidation interface, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 04/16] intel-iommu: add Intel IOMMU emulation to q35 and add a machine option "iommu" as a switch, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 07/16] intel-iommu: add context-cache to cache context-entry, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 05/16] intel-iommu: fix coding style issues around in q35.c and machine.c, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 09/16] vhost_net: cleanup start/stop condition, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 08/16] intel-iommu: add IOTLB using hash table, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 12/16] pci: avoid losing config updates to MSI/MSIX cap regs, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 10/16] ioh3420: remove unused ioh3420_init() declaration, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 14/16] vhost_net: init acked_features to backend_features, Michael S. Tsirkin, 2014/09/03
- [Qemu-devel] [PULL v2 15/16] vhost-scsi: init backend features earlier, Michael S. Tsirkin, 2014/09/03