Re: [Qemu-devel] [PATCH target-arm v4 2/7] arm: Implement PMCCNTR 32b read-modify-write

[Alistair Francis]

On Tue, Aug 26, 2014 at 2:10 PM, Peter Crosthwaite
<address@hidden> wrote:
> The register is now 64bit, however a 32 bit write to the register
> should leave the higher bits unchanged. The open coded write handler
> does not implement this, so we need to read-modify-write accordingly.
>
> Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
> ---
>
>  target-arm/helper.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 711ca12..0d2ee41 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -623,6 +623,15 @@ static void pmccntr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>      }
>      env->cp15.c15_ccnt = total_ticks - value;
>  }
> +
> +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
> +                            uint64_t value)
> +{
> +    uint64_t cur_val = pmccntr_read(env, NULL);
> +
> +    pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
> +}
> +
>  #endif
>

Looks good to me

>  static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -754,7 +763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>  #ifndef CONFIG_USER_ONLY
>      { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
>        .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
> -      .readfn = pmccntr_read, .writefn = pmccntr_write,
> +      .readfn = pmccntr_read, .writefn = pmccntr_write32,
>        .accessfn = pmreg_access },
>  #endif
>      { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 
> = 1,
> --
> 2.1.0.1.g27b9230
>