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Re: [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources |
Date: |
Mon, 25 Aug 2014 13:25:27 +0100 |
On 25 August 2014 10:16, Sergey Fedorov <address@hidden> wrote:
> On 22.08.2014 14:29, Fabian Aggeler wrote:
>> Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
>> Security Extensions.
>>
>> Signed-off-by: Fabian Aggeler <address@hidden>
>> ---
>> hw/intc/arm_gic.c | 3 +++
>> include/hw/intc/arm_gic_common.h | 1 +
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
>> index 1532ef9..b27bd0e 100644
>> --- a/hw/intc/arm_gic.c
>> +++ b/hw/intc/arm_gic.c
>> @@ -786,6 +786,9 @@ void gic_init_irqs_and_distributor(GICState *s, int
>> num_irq)
>> for (i = 0; i < NUM_CPU(s); i++) {
>> sysbus_init_irq(sbd, &s->parent_irq[i]);
>> }
>> + for (i = 0; i < NUM_CPU(s); i++) {
>> + sysbus_init_irq(sbd, &s->parent_fiq[i]);
>> + }
>
> Hi Fabian,
>
> I would suggest to provide a way to get a sysbus IRQ/FIQ number for each
> processor, e.g. a dedicated macro. Maybe it could be easier to
> accomplish this by initializing IRQ and FIQ interleaved or by always
> initializing GIC_NCPU IRQs/FIQs.
Using named GPIO registers is the way to go here,
or at least it will be once Peter C's patchset to make
sysbus IRQs just be legacy syntax for GPIOs goes in.
-- PMM
- [Qemu-devel] [PATCH 15/15] hw/intc/arm_gic: add gic_update() for grouping, (continued)
- [Qemu-devel] [PATCH 15/15] hw/intc/arm_gic: add gic_update() for grouping, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 10/15] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 04/15] hw/intc/arm_gic: Add ns_access() function, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 05/15] hw/intc/arm_gic: Add Interrupt Group Registers, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 06/15] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 08/15] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 12/15] hw/intc/arm_gic: Change behavior of IAR writes, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 11/15] hw/intc/arm_gic: Change behavior of EOIR writes, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 07/15] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 03/15] hw/intc/arm_gic: Add Security Extensions property, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 09/15] hw/intc/arm_gic: Implement Non-secure view of RPR, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 13/15] hw/intc/arm_gic: Restrict priority view, Fabian Aggeler, 2014/08/22
- [Qemu-devel] [PATCH 14/15] hw/intc/arm_gic: Break out gic_update() function, Fabian Aggeler, 2014/08/22