Re: [Qemu-devel] QEMU TCG can't Generate Hardware Floating Point Instructions?

[Peter Maydell]

On 11 August 2014 15:49, 傅 ㄏㄏ <address@hidden> wrote:
> I am studying some research about QEMU's TCG and also trace a part of code 
> translating TCG IRs to QEMU's host instructions recently.
> I found that TCG use integer instructions to simulate the guest's floating 
> point instructions instead of exploiting the FPU instructions supported by 
> the host.
> Is the reason in order to fit the result which the same program runs on the 
> simulated machine?

Yes. We must generate the exact same (bit-for-bit) result as the CPU
we are emulating, and also correctly generate the various exception
flags (overflow, underflow, etc) and handle edge cases like denormal
numbers and infinities in the right way. Since we also need to support
every possible combination of 16 guest CPU types and 8 host CPU
types, it's very difficult to make use of the host FPU. (Not impossible,
and it would make some workloads much faster, but it's hard enough
that nobody has tried to do it in a way that would be well engineered
and flexible enough for upstream.)

-- PMM