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Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and q
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu |
Date: |
Thu, 07 Aug 2014 16:28:58 -1000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.7.0 |
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
> + /* PSW flag cache for faster execution
> + if flag != 0 then flag is set. Else flag is not set.
> + */
> + target_ulong PSW_USB_C;
> + target_ulong PSW_USB_V;
> + target_ulong PSW_USB_SV;
> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
V and SV are also only set if bit 31 is set, the way we're computing overflow
from addition. Of course, overflow from saturation or multiplication isn't
being computed into bit 31, so there is a decision to make.
Depending on how important it is for ADDX+ADDC to be implemented efficiently,
vs how important is for SHA to be quick, you may wish to have C already set to
0/1 only.
r~
- [Qemu-devel] [PATCH v4 00/15] TriCore architecture guest implementation, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 05/15] target-tricore: Add masks and opcodes for decoding, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 07/15] target-tricore: Add instructions of SRR opcode format, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 06/15] target-tricore: Add instructions of SRC opcode format, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 08/15] target-tricore: Add instructions of SSR opcode format, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 10/15] target-tricore: Add instructions of SB opcode format, Bastian Koppelmann, 2014/08/07
- [Qemu-devel] [PATCH v4 11/15] target-tricore: Add instructions of SBC and SBRN opcode format, Bastian Koppelmann, 2014/08/07