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Re: [Qemu-devel] [PATCH v3 00/21] target-mips: add MIPS64R6 Instruction
From: |
Leon Alrae |
Subject: |
Re: [Qemu-devel] [PATCH v3 00/21] target-mips: add MIPS64R6 Instruction Set support |
Date: |
Tue, 5 Aug 2014 10:26:57 +0100 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
ping
http://patchwork.ozlabs.org/patch/365066/
http://patchwork.ozlabs.org/patch/365042/
http://patchwork.ozlabs.org/patch/365046/
http://patchwork.ozlabs.org/patch/365056/
http://patchwork.ozlabs.org/patch/365059/
On 27/06/2014 16:21, Leon Alrae wrote:
> The following patchset implements MIPS64 Release 6 Instruction Set.
> New instructions are added and also there is a number of instructions which
> are deleted or moved (the encodings have changed).
>
> The MIPS64 Release 6 documentation is available:
> http://www.imgtec.com/mips/architectures/mips64.asp
>
> The following patch series is focusing on instruction set changes only.
> There is also a new generic cpu supporting R6.
>
> Please note that even though the new Floating Point instructions were added,
> softfloat for MIPS has not been updated yet (in R6 MIPS FPU is updated to
> IEEE2008). Also, current patchset does not include MIPS64 Privileged Resource
> Architecture modifications. All those changes will follow the current patchset
> soon.
>
> v3:
> * addressed further comments and suggestions (more detailed changelog included
> in the separate patches).
> * dropped patch adding function pointers due to its doubtful usefulness
> * rebased
> v2:
> * addressed all comments so far from Richard and Aurelien. More detailed
> changelog included in the separate patches.
> * added missing zero register case for LSA, ALIGN and BITSWAP instructions
>
> Leon Alrae (17):
> target-mips: define ISA_MIPS64R6
> target-mips: signal RI Exception on instructions removed in R6
> target-mips: add SELEQZ and SELNEZ instructions
> target-mips: move LL and SC instructions
> target-mips: extract decode_opc_special* from decode_opc
> target-mips: split decode_opc_special* into *_r6 and *_legacy
> target-mips: signal RI Exception on DSP and Loongson instructions
> target-mips: move PREF, CACHE, LLD and SCD instructions
> target-mips: redefine Integer Multiply and Divide instructions
> target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6
> target-mips: Status.UX/SX/KX enable 32-bit address wrapping
> target-mips: add AUI, LSA and PCREL instruction families
> softfloat: add functions corresponding to IEEE-2008 min/maxNumMag
> target-mips: add new Floating Point instructions
> target-mips: do not allow Status.FR=0 mode in 64-bit FPU
> mips_malta: update malta's pseudo-bootloader - replace JR with JALR
> target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA
>
> Yongbok Kim (4):
> target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions
> target-mips: add compact and CP1 branches
> target-mips: add new Floating Point Comparison instructions
> target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions
>
> disas/mips.c | 211 +++-
> fpu/softfloat.c | 37 +-
> hw/mips/mips_malta.c | 10 +-
> include/fpu/softfloat.h | 4 +
> target-mips/cpu.h | 18 +-
> target-mips/helper.h | 52 +
> target-mips/mips-defs.h | 28 +-
> target-mips/op_helper.c | 238 +++
> target-mips/translate.c | 3814
> +++++++++++++++++++++++++++++++-----------
> target-mips/translate_init.c | 30 +
> 10 files changed, 3430 insertions(+), 1012 deletions(-)
>
- Re: [Qemu-devel] [PATCH v3 00/21] target-mips: add MIPS64R6 Instruction Set support,
Leon Alrae <=