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[Qemu-devel] [PATCH v3 11/15] target-tricore: Add instructions of SBC an
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v3 11/15] target-tricore: Add instructions of SBC and SBRN opcode format |
Date: |
Mon, 4 Aug 2014 18:38:48 +0100 |
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ffc524b..6cbfe89 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -365,6 +365,8 @@ static inline void gen_branch_condi(DisasContext *ctx, int
cond, TCGv r1,
static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
int r2 , int32_t constant , int32_t offset)
{
+ TCGv temp;
+
switch (opc) {
/* SB-format jumps */
case OPC1_16_SB_J:
@@ -380,6 +382,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t
opc, int r1,
case OPC1_16_SB_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
break;
+/* SBC-format jumps */
+ case OPC1_16_SBC_JEQ:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+ case OPC1_16_SBC_JNE:
+ gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+ break;
+/* SBRN-format jumps */
+ case OPC1_16_SBRN_JZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SBRN_JNZ_T:
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+ gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
+ tcg_temp_free(temp);
+ break;
default:
printf("Branch Error at %x\n", ctx->pc);
}
@@ -683,6 +705,20 @@ static void decode_16Bit_opc(CPUTRICOREState *env,
DisasContext *ctx)
address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, 0, address);
break;
+/* SBC-format */
+ case OPC1_16_SBC_JEQ:
+ case OPC1_16_SBC_JNE:
+ address = MASK_OP_SBC_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
+/* SBRN-format */
+ case OPC1_16_SBRN_JNZ_T:
+ case OPC1_16_SBRN_JZ_T:
+ address = MASK_OP_SBRN_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBRN_N(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address);
+ break;
}
}
--
2.0.4
- [Qemu-devel] [PATCH v3 00/15] TriCore architecture guest implementation, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 01/15] target-tricore: Add target stubs and qom-cpu, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 11/15] target-tricore: Add instructions of SBC and SBRN opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v3 07/15] target-tricore: Add instructions of SRR opcode format, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 03/15] target-tricore: Add softmmu support, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 10/15] target-tricore: Add instructions of SB opcode format, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 08/15] target-tricore: Add instructions of SSR opcode format, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 02/15] target-tricore: Add board for systemmode, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 04/15] target-tricore: Add initialization for translation and activate target, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 13/15] target-tricore: Add instructions of SC opcode format, Bastian Koppelmann, 2014/08/04
- [Qemu-devel] [PATCH v3 06/15] target-tricore: Add instructions of SRC opcode format, Bastian Koppelmann, 2014/08/04