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[Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3 |
Date: |
Mon, 4 Aug 2014 14:53:24 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b755f99..3d9cf57 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -185,7 +185,7 @@ typedef struct CPUARMState {
uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
uint32_t ifsr_el2; /* Fault status registers. */
- uint64_t esr_el[2];
+ uint64_t esr_el[4];
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[2]; /* Fault address registers. */
uint64_t par_el1; /* Translation result. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b5f2e57..f4845b0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2127,6 +2127,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
.access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, elr_el[2]) },
+ { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
{ .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
@@ -2145,6 +2149,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
.access = PL3_RW,
.fieldoffset = offsetof(CPUARMState, elr_el[3]) },
+ { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
{ .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
--
1.9.1
- [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 11/12] target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 12/12] target-arm: A64: fix TLB flush instructions, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 10/12] target-arm: Fix bit test in sp_el0_access, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 02/12] hw/arm/virt: formatting: memory map, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 03/12] sd: sdhci: Fix ADMA dma_memory_read access, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 08/12] target-arm: Add ESR_EL2 and 3,
Peter Maydell <=
- [Qemu-devel] [PULL 06/12] target-arm: A64: Respect SPSEL when taking exceptions, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 09/12] target-arm: Add FAR_EL2 and 3, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 01/12] hw/arm/boot: Set PC correctly when loading AArch64 ELF files, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 07/12] target-arm: Make far_el1 an array, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 05/12] target-arm: A64: Respect SPSEL in ERET SP restore, Peter Maydell, 2014/08/04
- [Qemu-devel] [PULL 04/12] target-arm: A64: Break out aarch64_save/restore_sp, Peter Maydell, 2014/08/04
- Re: [Qemu-devel] [PULL 00/12] target-arm queue, Peter Maydell, 2014/08/04