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From: | Elta |
Subject: | Re: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Add judgement for msb and lsb |
Date: | Tue, 29 Jul 2014 20:41:08 +0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 07/29/2014 06:52 AM, Aurelien Jarno wrote:
On Mon, Jul 28, 2014 at 11:34:30PM +0100, Peter Maydell wrote:On 28 July 2014 23:32, Aurelien Jarno <address@hidden> wrote:On Mon, Jul 28, 2014 at 11:01:02PM +0100, Peter Maydell wrote:This may be true, but the TCG README doesn't define negative lengths as being "unspecified behaviour" (ie guaranteed to at least not crash even if the result isn't specified), and in fact the implementation of tcg_gen_deposit will assert on negative lengths. We shouldn't implement guest unpredictable cases as "crash QEMU".Well I tried this code under QEMU, and it clearly doesn't crash. It seems the assert are not enabled with the default configuration options.Try --enable-debug...That's my point, it's only in debug mode, not in the default configuration.
Maybe remove the tcg_debug_assert in tcg_gen_deposit_i64 and tcg_gen_deposit_i64 is a better way. But it may cause other mistake in other architecture, i'm not
sure.
I think, debug mode shouldn't crash the qemu with an unpredictable operation,That said I agree it's something to avoid, but I don't think triggering a RI exception is the thing to do (even if it is correct according the MIPS ISA manual) when real silicon output a random result instead.Yes, you could emit code to do that instead if you like.When I said random, it didn't say in the sense of random generator, but in the sense a result that might depend on the input value and the silicon implementation. It would be silly to emit code just for that, but it would be smart for example to skip the deposit op in that case instead of triggering an exception.
so i want to fix it. And you say there shouldn't raise RI, i agree with you.Or when lsb > msb, just leave the code and do nothing. What do you think about
this way?
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