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[Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h
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From: |
Yongbok Kim |
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Subject: |
[Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h |
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Date: |
Mon, 14 Jul 2014 10:55:46 +0100 |
move commonly used functions to cpu.h
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/cpu.h | 72 +++++++++++++++++++++++++++++++++++++++++++++++
target-mips/gdbstub.c | 7 ----
target-mips/op_helper.c | 60 +-------------------------------------
3 files changed, 74 insertions(+), 65 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9a6b77c..68ce383 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -747,6 +747,10 @@ hwaddr cpu_mips_translate_address (CPUMIPSState *env,
target_ulong address,
#endif
target_ulong exception_resume_pc (CPUMIPSState *env);
+/* op_helper.c */
+extern unsigned int ieee_rm[];
+int ieee_ex_to_mips(int xcpt);
+
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
@@ -859,4 +863,72 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
+#include "exec/cpu_ldst.h"
+
+#if defined(CONFIG_USER_ONLY)
+#define HELPER_LD(name, insn, type) \
+static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
+ int mem_idx) \
+{ \
+ return (type) insn##_raw(addr); \
+}
+#else
+#define HELPER_LD(name, insn, type) \
+static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
+ int mem_idx) \
+{ \
+ switch (mem_idx) { \
+ case 0: \
+ return (type) cpu_##insn##_kernel(env, addr); \
+ break; \
+ case 1: \
+ return (type) cpu_##insn##_super(env, addr); \
+ break; \
+ default: \
+ case 2: \
+ return (type) cpu_##insn##_user(env, addr); \
+ break; \
+ } \
+}
+#endif
+HELPER_LD(lbu, ldub, uint8_t)
+HELPER_LD(lw, ldl, int32_t)
+#ifdef TARGET_MIPS64
+HELPER_LD(ld, ldq, int64_t)
+#endif
+#undef HELPER_LD
+
+#if defined(CONFIG_USER_ONLY)
+#define HELPER_ST(name, insn, type) \
+static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
+ type val, int mem_idx) \
+{ \
+ insn##_raw(addr, val); \
+}
+#else
+#define HELPER_ST(name, insn, type) \
+static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
+ type val, int mem_idx) \
+{ \
+ switch (mem_idx) { \
+ case 0: \
+ cpu_##insn##_kernel(env, addr, val); \
+ break; \
+ case 1: \
+ cpu_##insn##_super(env, addr, val); \
+ break; \
+ default: \
+ case 2: \
+ cpu_##insn##_user(env, addr, val); \
+ break; \
+ } \
+}
+#endif
+HELPER_ST(sb, stb, uint8_t)
+HELPER_ST(sw, stl, uint32_t)
+#ifdef TARGET_MIPS64
+HELPER_ST(sd, stq, uint64_t)
+#endif
+#undef HELPER_ST
+
#endif /* !defined (__MIPS_CPU_H__) */
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 5b72d58..f65fec2 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -73,13 +73,6 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
return 0;
}
-/* convert MIPS rounding mode in FCR31 to IEEE library */
-static unsigned int ieee_rm[] = {
- float_round_nearest_even,
- float_round_to_zero,
- float_round_up,
- float_round_down
-};
#define RESTORE_ROUNDING_MODE \
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], \
&env->active_fpu.fp_status)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 75f8af8..b47e2c8 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -68,62 +68,6 @@ void helper_raise_exception(CPUMIPSState *env, uint32_t
exception)
do_raise_exception(env, exception, 0);
}
-#if defined(CONFIG_USER_ONLY)
-#define HELPER_LD(name, insn, type) \
-static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
- int mem_idx) \
-{ \
- return (type) insn##_raw(addr); \
-}
-#else
-#define HELPER_LD(name, insn, type) \
-static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
- int mem_idx) \
-{ \
- switch (mem_idx) \
- { \
- case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
- case 1: return (type) cpu_##insn##_super(env, addr); break; \
- default: \
- case 2: return (type) cpu_##insn##_user(env, addr); break; \
- } \
-}
-#endif
-HELPER_LD(lbu, ldub, uint8_t)
-HELPER_LD(lw, ldl, int32_t)
-#ifdef TARGET_MIPS64
-HELPER_LD(ld, ldq, int64_t)
-#endif
-#undef HELPER_LD
-
-#if defined(CONFIG_USER_ONLY)
-#define HELPER_ST(name, insn, type) \
-static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
- type val, int mem_idx) \
-{ \
- insn##_raw(addr, val); \
-}
-#else
-#define HELPER_ST(name, insn, type) \
-static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
- type val, int mem_idx) \
-{ \
- switch (mem_idx) \
- { \
- case 0: cpu_##insn##_kernel(env, addr, val); break; \
- case 1: cpu_##insn##_super(env, addr, val); break; \
- default: \
- case 2: cpu_##insn##_user(env, addr, val); break; \
- } \
-}
-#endif
-HELPER_ST(sb, stb, uint8_t)
-HELPER_ST(sw, stl, uint32_t)
-#ifdef TARGET_MIPS64
-HELPER_ST(sd, stq, uint64_t)
-#endif
-#undef HELPER_ST
-
target_ulong helper_clo (target_ulong arg1)
{
return clo32(arg1);
@@ -2185,7 +2129,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
/* convert MIPS rounding mode in FCR31 to IEEE library */
-static unsigned int ieee_rm[] = {
+unsigned int ieee_rm[] = {
float_round_nearest_even,
float_round_to_zero,
float_round_up,
@@ -2301,7 +2245,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1,
uint32_t fs, uint32_t rt)
do_raise_exception(env, EXCP_FPE, GETPC());
}
-static inline int ieee_ex_to_mips(int xcpt)
+int ieee_ex_to_mips(int xcpt)
{
int ret = 0;
if (xcpt) {
--
1.7.4
- [Qemu-devel] [PATCH 00/20] target-mips: add MSA module, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 01/20] target-mips: add MSA defines and data structure, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 05/20] target-mips: stop translation after ctc1, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 04/20] target-mips: add 8, 16, 32, 64 bits load and store, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 08/20] target-mips: add msa_helper.c, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h,
Yongbok Kim <=
- [Qemu-devel] [PATCH 09/20] target-mips: add MSA branch instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 02/20] target-mips: add MSA exceptions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 10/20] target-mips: add MSA I8 format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 11/20] target-mips: add MSA I5 format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 12/20] target-mips: add MSA BIT format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 14/20] target-mips: add MSA ELM format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 16/20] target-mips: add MSA VEC/2R format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 18/20] target-mips: add MSA MI10 format instructions, Yongbok Kim, 2014/07/14
- [Qemu-devel] [PATCH 15/20] target-mips: add MSA 3RF format instructions, Yongbok Kim, 2014/07/14