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Re: [Qemu-devel] [PATCH v3 00/16] target-arm: Parts of the AArch64 EL2/3
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH v3 00/16] target-arm: Parts of the AArch64 EL2/3 exception model |
Date: |
Fri, 11 Jul 2014 09:17:52 +1000 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
Ping!
PMM, are you expecting me to change something with this series that I've
missed or is it just busy times for review?
Cheers,
Edgar
On Tue, Jun 17, 2014 at 06:45:30PM +1000, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Hi,
>
> This is a second round of AArch64 EL2/3 patches working on the exception
> model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
> Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
> delivery method.
>
> Patch 3 is a bug fix.
> Patch 14 fails checkpatch, seems like a bug in checkpatch, CC:d Blue.
>
> This conflicts slightly with the PSCI emulation patches that Rob posted.
> A rebase should be trivial, hooking in the PSCI emulation calls in the
> HVC/SMC helpers.
>
> Cheers,
> Edgar
>
> v2 -> v3:
> * Add more HCR bitfield macros
> * Flush TLB on hcr_write change of HCR RW, DC and PTW.
> * Fix hvc helper, HVC is undefined in secure mode.
> * Remove uint16_t imm16 syndrome gen change.
> * Replace c1_scr with scr_el3
>
> v1 -> v2:
> * Avoid imm16 mask in syndrome generation
> * Use g_assert_not_reached() in arm_excp_unmasked()
> * Avoid some logic duplication in arm_excp_target_el and arm_excp_unmasked.
> * Put arm_excp_target_el in helper.c to start with.
> * Fix SMC disable (SMD or SCD) for ARMv7 only applies if EL2 exists
> * SCR_RES0_MASK -> SCR_MASK
> * HCR_RES0_MASK -> HCR_MASK
> * Fix SMC routing to EL2, only applies for NS EL1.
> * Fix CPreg defs for ESR_EL2/3
> * Fix SMC helper, SMC routing to EL2 and SCR.SMD for AArch32.
>
> Edgar E. Iglesias (16):
> target-arm: A64: Break out aarch64_save/restore_sp
> target-arm: A64: Respect SPSEL in ERET SP restore
> target-arm: A64: Respect SPSEL when taking exceptions
> target-arm: Make far_el1 an array
> target-arm: Add ESR_EL2 and 3
> target-arm: Add FAR_EL2 and 3
> target-arm: Add HCR_EL2
> target-arm: Add SCR_EL3
> target-arm: A64: Refactor aarch64_cpu_do_interrupt
> target-arm: Break out exception masking to a separate func
> target-arm: Don't take interrupts targeting lower ELs
> target-arm: A64: Correct updates to FAR and ESR on exceptions
> target-arm: A64: Emulate the HVC insn
> target-arm: A64: Emulate the SMC insn
> target-arm: Add IRQ and FIQ routing to EL2 and 3
> target-arm: Add support for VIRQ and VFIQ
>
> cpu-exec.c | 17 +++++-
> target-arm/cpu.c | 22 ++++++-
> target-arm/cpu.h | 120 ++++++++++++++++++++++++++++++++++++-
> target-arm/helper-a64.c | 32 +++++-----
> target-arm/helper.c | 145
> ++++++++++++++++++++++++++++++++++++++++++---
> target-arm/helper.h | 2 +
> target-arm/internals.h | 43 +++++++++++---
> target-arm/kvm64.c | 13 +---
> target-arm/op_helper.c | 68 +++++++++++++++++++--
> target-arm/translate-a64.c | 31 ++++++++--
> 10 files changed, 433 insertions(+), 60 deletions(-)
>
> --
> 1.8.3.2
>
- Re: [Qemu-devel] [PATCH v3 00/16] target-arm: Parts of the AArch64 EL2/3 exception model,
Edgar E. Iglesias <=