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[Qemu-devel] [PULL 4/8] hw/arm/pxa2xx_gpio: Fix handling of GPSR/GPCR re
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/8] hw/arm/pxa2xx_gpio: Fix handling of GPSR/GPCR reads |
Date: |
Mon, 30 Jun 2014 13:47:27 +0100 |
The PXA2xx GPIO GPSR and GPCR registers are write-only, with reads being
undefined behaviour. Instead of having GPCR return 31337 and GPSR return
the value last written, make both log the guest error and return 0.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
hw/arm/pxa2xx_gpio.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
index 7f75f05..cd506df 100644
--- a/hw/arm/pxa2xx_gpio.c
+++ b/hw/arm/pxa2xx_gpio.c
@@ -36,7 +36,6 @@ struct PXA2xxGPIOInfo {
uint32_t rising[PXA2XX_GPIO_BANKS];
uint32_t falling[PXA2XX_GPIO_BANKS];
uint32_t status[PXA2XX_GPIO_BANKS];
- uint32_t gpsr[PXA2XX_GPIO_BANKS];
uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
uint32_t prev_level[PXA2XX_GPIO_BANKS];
@@ -162,14 +161,14 @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr
offset,
return s->dir[bank];
case GPSR: /* GPIO Pin-Output Set registers */
- printf("%s: Read from a write-only register " REG_FMT "\n",
- __FUNCTION__, offset);
- return s->gpsr[bank]; /* Return last written value. */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pxa2xx GPIO: read from write only register GPSR\n");
+ return 0;
case GPCR: /* GPIO Pin-Output Clear registers */
- printf("%s: Read from a write-only register " REG_FMT "\n",
- __FUNCTION__, offset);
- return 31337; /* Specified as unpredictable in the docs. */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pxa2xx GPIO: read from write only register GPCR\n");
+ return 0;
case GRER: /* GPIO Rising-Edge Detect Enable registers */
return s->rising[bank];
@@ -217,7 +216,6 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
case GPSR: /* GPIO Pin-Output Set registers */
s->olevel[bank] |= value;
pxa2xx_gpio_handler_update(s);
- s->gpsr[bank] = value;
break;
case GPCR: /* GPIO Pin-Output Clear registers */
--
1.9.1
- [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 2/8] hw/arm/strongarm: Fix handling of GPSR/GPCR reads, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 3/8] hw/arm/strongarm: Wire up missing GPIO and PPC vmstate, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 5/8] hw/arm/pxa2xx_gpio: Correct and register vmstate, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 4/8] hw/arm/pxa2xx_gpio: Fix handling of GPSR/GPCR reads,
Peter Maydell <=
- [Qemu-devel] [PULL 1/8] hw/arm/virt: Provide PL031 RTC, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 7/8] disas/libvixl: Update README for version base, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 8/8] disas/libvixl: Fix wrong format strings, Peter Maydell, 2014/06/30
- [Qemu-devel] [PULL 6/8] timer: cadence_ttc: Convert to instance_init, Peter Maydell, 2014/06/30
- Re: [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2014/06/30