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Re: [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-boot
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR |
Date: |
Thu, 19 Jun 2014 23:27:15 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Wed, Jun 11, 2014 at 04:19:50PM +0100, Leon Alrae wrote:
> JR has been removed in R6 and now this instruction will cause Reserved
> Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
>
> Signed-off-by: Leon Alrae <address@hidden>
> ---
> hw/mips/mips_malta.c | 10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index f4a7d47..72071c0 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -694,12 +694,12 @@ static void write_bootloader (CPUMIPSState *env,
> uint8_t *base,
> /* Jump to kernel code */
> stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra,
> high(kernel_entry) */
> stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra,
> ra, low(kernel_entry) */
> - stl_p(p++, 0x03e00008); /* jr ra */
> + stl_p(p++, 0x03e00009); /* jalr ra
> */
> stl_p(p++, 0x00000000); /* nop */
>
> /* YAMON subroutines */
> p = (uint32_t *) (base + 0x800);
> - stl_p(p++, 0x03e00008); /* jr ra */
> + stl_p(p++, 0x03e00009); /* jalr ra */
> stl_p(p++, 0x24020000); /* li v0,0 */
> /* 808 YAMON print */
> stl_p(p++, 0x03e06821); /* move
> t5,ra */
> @@ -713,7 +713,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t
> *base,
> stl_p(p++, 0x00000000); /* nop */
> stl_p(p++, 0x08000205); /* j 814 */
> stl_p(p++, 0x00000000); /* nop */
> - stl_p(p++, 0x01a00008); /* jr t5 */
> + stl_p(p++, 0x01a00009); /* jalr t5 */
> stl_p(p++, 0x01602021); /* move
> a0,t3 */
> /* 0x83c YAMON print_count */
> stl_p(p++, 0x03e06821); /* move
> t5,ra */
> @@ -727,7 +727,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t
> *base,
> stl_p(p++, 0x258cffff); /* addiu
> t4,t4,-1 */
> stl_p(p++, 0x1580fffa); /* bnez
> t4,84c */
> stl_p(p++, 0x00000000); /* nop */
> - stl_p(p++, 0x01a00008); /* jr t5 */
> + stl_p(p++, 0x01a00009); /* jalr t5 */
> stl_p(p++, 0x01602021); /* move
> a0,t3 */
> /* 0x870 */
> stl_p(p++, 0x3c08b800); /* lui
> t0,0xb400 */
> @@ -737,7 +737,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t
> *base,
> stl_p(p++, 0x31290040); /* andi
> t1,t1,0x40 */
> stl_p(p++, 0x1120fffc); /* beqz
> t1,878 <outch+0x8> */
> stl_p(p++, 0x00000000); /* nop */
> - stl_p(p++, 0x03e00008); /* jr ra */
> + stl_p(p++, 0x03e00009); /* jalr ra */
> stl_p(p++, 0xa1040000); /* sb
> a0,0(t0) */
>
Reviewed-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- Re: [Qemu-devel] [PATCH v2 12/22] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions, (continued)
- [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-relative instructions, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 17/22] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 16/22] target-mips: add new Floating Point instructions, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 19/22] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 22/22] target-mips: define a new generic CPU supporting MIPS64R6, Leon Alrae, 2014/06/11
- [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/06/11
- Re: [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 15/22] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, Leon Alrae, 2014/06/11