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[Qemu-devel] [PATCH 2/9] target-arm: Remove unnecessary setting of featu
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 2/9] target-arm: Remove unnecessary setting of feature bits |
Date: |
Fri, 30 May 2014 14:55:18 +0100 |
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so
we don't need to set them explicitly in initfns which set the
V8 feature bit.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 2 --
target-arm/cpu64.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 94123b2..383e22a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -960,8 +960,6 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
- set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_CRC);
cpu->midr = 0xffffffff;
}
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 8daa622..c151dea 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -139,8 +139,6 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
- set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
--
1.9.2
- [Qemu-devel] [PATCH 0/9] target-arm: A64: Implement crypto insns, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 4/9] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 2/9] target-arm: Remove unnecessary setting of feature bits,
Peter Maydell <=
- [Qemu-devel] [PATCH 1/9] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 9/9] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 3/9] target-arm: Clean up handling of ARMv8 optional feature bits, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 8/9] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 6/9] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 5/9] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 7/9] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/05/30