[Qemu-devel] [PATCH] target-mips: copy CP0_Config1 into DisasContext

[Aurelien Jarno]

In order to avoid access to the CPUMIPSState structure in the
translator, keep a copy of CP0_Config1 into DisasContext. The whole
register is read-only so it can be copied as a single value.

Signed-off-by: Aurelien Jarno <address@hidden>
---
 target-mips/translate.c |   20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 13cf29b..bb89413 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1066,6 +1066,7 @@ typedef struct DisasContext {
     uint32_t opcode;
     int singlestep_enabled;
     int insn_flags;
+    int32_t CP0_Config1;
     /* Routine used to access memory */
     int mem_idx;
     uint32_t hflags, saved_hflags;
@@ -1919,10 +1920,10 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t 
opc, int ft,
     tcg_temp_free(t0);
 }
 
-static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx,
-                          uint32_t op, int rt, int rs, int16_t imm)
+static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
+                          int rs, int16_t imm)
 {
-    if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+    if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
         check_cp1_enabled(ctx);
         gen_flt_ldst(ctx, op, rt, rs, imm);
     } else {
@@ -11789,7 +11790,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, 
DisasContext *ctx,
         }
         break;
     case POOL32F:
-        if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+        if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
             minor = ctx->opcode & 0x3f;
             check_cp1_enabled(ctx);
             switch (minor) {
@@ -12303,7 +12304,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, 
DisasContext *ctx,
     case SDC132:
         mips32_op = OPC_SDC1;
     do_cop1:
-        gen_cop1_ldst(env, ctx, mips32_op, rt, rs, imm);
+        gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
         break;
     case ADDIUPC:
         {
@@ -14551,7 +14552,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext 
*ctx)
 
         case OPC_MOVCI:
             check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
-            if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+            if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
                 check_cp1_enabled(ctx);
                 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
                           (ctx->opcode >> 16) & 1);
@@ -15430,11 +15431,11 @@ static void decode_opc (CPUMIPSState *env, 
DisasContext *ctx)
     case OPC_LDC1:
     case OPC_SWC1:
     case OPC_SDC1:
-        gen_cop1_ldst(env, ctx, op, rt, rs, imm);
+        gen_cop1_ldst(ctx, op, rt, rs, imm);
         break;
 
     case OPC_CP1:
-        if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+        if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
             check_cp1_enabled(ctx);
             op1 = MASK_CP1(ctx->opcode);
             switch (op1) {
@@ -15496,7 +15497,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext 
*ctx)
         break;
 
     case OPC_CP3:
-        if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+        if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
             check_cp1_enabled(ctx);
             op1 = MASK_CP3(ctx->opcode);
             switch (op1) {
@@ -15604,6 +15605,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, 
TranslationBlock *tb,
     ctx.saved_pc = -1;
     ctx.singlestep_enabled = cs->singlestep_enabled;
     ctx.insn_flags = env->insn_flags;
+    ctx.CP0_Config1 = env->CP0_Config1;
     ctx.tb = tb;
     ctx.bstate = BS_NONE;
     /* Restore delay slot state from the tb context.  */
-- 
1.7.10.4