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Re: [Qemu-devel] [v2 PATCH] target-mips: implement UserLocal Register


From: Petar Jovanovic
Subject: Re: [Qemu-devel] [v2 PATCH] target-mips: implement UserLocal Register
Date: Thu, 29 May 2014 00:49:16 +0000

>> make it accessable to unprivileged software via register 29 (ULR) of the
> "accessible"

Fixed in v3.

>  static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
> @@ -173,6 +174,7 @@ static void load_tc(QEMUFile *f, TCState *tc)
>      qemu_get_betls(f, &tc->CP0_TCSchedule);
>      qemu_get_betls(f, &tc->CP0_TCScheFBack);
>      qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
> +    qemu_get_betls(f, &tc->CP0_UserLocal);
>  }
>  
>  static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)

> You can't just add fields here. When loading you'll need to check the
> version you're loading for whether or not to load the field, and for
> saving you need to increment the version.

Fixed in v3, thanks.

Regards,
Petar
________________________________________
From: Andreas Färber address@hidden
Sent: Monday, May 26, 2014 11:18 PM
To: Petar Jovanovic; address@hidden
Cc: James Hogan; Petar Jovanovic; address@hidden; address@hidden
Subject: Re: [Qemu-devel] [v2 PATCH] target-mips: implement UserLocal Register

Am 26.05.2014 19:28, schrieb Petar Jovanovic:
> From: Petar Jovanovic <address@hidden>
>
> From MIPS documentation (Volume III):
>
> UserLocal Register (CP0 Register 4, Select 2)
> Compliance Level: Recommended.
>
> The UserLocal register is a read-write register that is not interpreted by
> the hardware and conditionally readable via the RDHWR instruction.
>
> This register only exists if the Config3-ULRI register field is set.
>
> Privileged software may write this register with arbitrary information and
> make it accessable to unprivileged software via register 29 (ULR) of the

"accessible"

> RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a
> 1 to enable unprivileged access to the register.
>
> Signed-off-by: Petar Jovanovic <address@hidden>
> ---
> v2:
> - Defined MIPS_HFLAG_CP0UL flag, checks are now based on hflags
> - CP0_UserLocal moved to struct TCState
> - Added tc->CP0_UserLocal in save_tc/load_tc in target-mips/machine.c
> - Reused CP0_UserLocal field for user-mode purpose
[...]
> diff --git a/target-mips/machine.c b/target-mips/machine.c
> index 0a07db8..cbd9d7a 100644
> --- a/target-mips/machine.c
> +++ b/target-mips/machine.c
> @@ -25,6 +25,7 @@ static void save_tc(QEMUFile *f, TCState *tc)
>      qemu_put_betls(f, &tc->CP0_TCSchedule);
>      qemu_put_betls(f, &tc->CP0_TCScheFBack);
>      qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
> +    qemu_put_betls(f, &tc->CP0_UserLocal);
>  }
>
>  static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
> @@ -173,6 +174,7 @@ static void load_tc(QEMUFile *f, TCState *tc)
>      qemu_get_betls(f, &tc->CP0_TCSchedule);
>      qemu_get_betls(f, &tc->CP0_TCScheFBack);
>      qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
> +    qemu_get_betls(f, &tc->CP0_UserLocal);
>  }
>
>  static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)

You can't just add fields here. When loading you'll need to check the
version you're loading for whether or not to load the field, and for
saving you need to increment the version.

Otherwise looks sensible.

Regards,
Andreas

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