[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transit
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transition |
Date: |
Tue, 13 May 2014 14:57:24 +0200 |
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.
This bug is masked right now because a full reset will clear the
value of port 92h. But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.
Reviewed-by: Anthony Liguori <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/i386/pc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 07de238..e6369d5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -471,11 +471,12 @@ static void port92_write(void *opaque, hwaddr addr,
uint64_t val,
unsigned size)
{
Port92State *s = opaque;
+ int oldval = s->outport;
DPRINTF("port92: write 0x%02x\n", val);
s->outport = val;
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
- if (val & 1) {
+ if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request();
}
}
--
1.8.3.1
- [Qemu-devel] [PULL 05/15] target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c, (continued)
- [Qemu-devel] [PULL 05/15] target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 06/15] target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 07/15] target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 08/15] target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly., Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 11/15] target-i386: fix set of registers zeroed on reset, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 12/15] target-i386: preserve FPU and MSR state on INIT, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 09/15] kvm: reset state from the CPU's reset method, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 13/15] apic: do not accept SIPI on the bootstrap processor, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 10/15] kvm: forward INIT signals coming from the chipset, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 14/15] cpu: make CPU_INTERRUPT_RESET available on all targets, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transition,
Paolo Bonzini <=
- Re: [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13, Peter Maydell, 2014/05/15
- Re: [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13, Andreas Färber, 2014/05/15