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[Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register |
Date: |
Thu, 8 May 2014 11:35:07 +1000 |
From: Guenter Roeck <address@hidden>
The TCSR register has only 11 valid bits. This is now used by the
linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits
before writing the register to solve the problem.
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
hw/timer/xilinx_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 6113b97..3ff1da9 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
if (value & TCSR_TINT)
value &= ~TCSR_TINT;
- xt->regs[addr] = value;
+ xt->regs[addr] = value & 0x7ff;
if (value & TCSR_ENT)
timer_enable(xt);
break;
--
1.8.3.2