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[Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mo
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc |
Date: |
Thu, 17 Apr 2014 11:33:50 +0100 |
The AArch64 implementation of the set_pc method needs to be updated to
handle the possibility that the CPU is in AArch32 mode; otherwise there
are weird crashes when doing interprocessing in system emulation mode
when an interrupt occurs and we fail to resynchronize the 32-bit PC
with the TB we need to execute next.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 9a0c431..c673ac2 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -172,11 +172,15 @@ static void aarch64_cpu_finalizefn(Object *obj)
static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
- /*
- * TODO: this will need updating for system emulation,
- * when the core may be in AArch32 mode.
+ /* It's OK to look at env for the current mode here, because it's
+ * never possible for an AArch64 TB to chain to an AArch32 TB.
+ * (Otherwise we would need to use synchronize_from_tb instead.)
*/
- cpu->env.pc = value;
+ if (is_a64(&cpu->env)) {
+ cpu->env.pc = value;
+ } else {
+ cpu->env.regs[15] = value;
+ }
}
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
--
1.9.1
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, (continued)
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc,
Peter Maydell <=
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 31/51] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 28/51] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 26/51] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 20/51] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/17