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[Qemu-devel] [PATCH v6 11/37] target-arm: Don't mention PMU in debug fea
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 11/37] target-arm: Don't mention PMU in debug feature register |
Date: |
Thu, 10 Apr 2014 17:15:10 +0100 |
Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific
value claims that it exists. QEMU doesn't currently implement it,
and not advertising it prevents the guest from trying to use it
and getting UNDEFs on unimplemented registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
This is arguably a hack, but otherwise Linux tries to prod
half a dozen PMU sysregs.
---
target-arm/helper.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4b6c1b6..62f7fd3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2036,7 +2036,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64dfr0 },
+ /* We mask out the PMUVer field, beacuse we don't currently
+ * implement the PMU. Not advertising it prevents the guest
+ * from trying to use it and getting UNDEFs on registers we
+ * don't implement.
+ */
+ .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
--
1.9.1
- Re: [Qemu-devel] [PATCH v6 19/37] target-arm: Implement AArch64 EL1 exception handling, (continued)
- [Qemu-devel] [PATCH v6 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 26/37] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 01/37] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 11/37] target-arm: Don't mention PMU in debug feature register,
Peter Maydell <=
- [Qemu-devel] [PATCH v6 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 10/37] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 18/37] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/10