Re: [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs

[Andreas Färber]

Am 31.03.2014 03:25, schrieb Alexey Kardashevskiy:
> On 03/24/2014 05:24 PM, Alexey Kardashevskiy wrote:
>> btw while grepping through the code, I found dump_ppc_sprs() which prints
>> this (first chunk is what my patch adds and the second chunk is from
>> dump_ppc_sprs()):
> 
> 
> 
> Noone has an opinion? Come on! :)

We're in Hard Freeze!!! >:-| There's more important works than post-2.0
debug infos ATM. Anyway...

>> XER    0000000000000000 LR     0000000000000000 CTR    0000000000000000
>> UAMR   0000000000000000
>> DSCR   0000000000000000 DSISR  0000000000000000 DAR    0000000000000000
>> DECR   0000000000000000
>> SDR1   0000000000000005 SRR0   0000000000000000 SRR1   0000000000000000
>> CFAR   0000000000000000
>> AMR    0000000000000000 CTRLF  0000000080800000 CTRLT  0000000080800000
>> UAMOR  0000000000000000
>> VRSAVE 0000000000000000 TBL    0000000000000000 TBU    0000000000000000
>> SPRG0  0000000000000000
>> SPRG1  0000000000000000 SPRG2  0000000000000000 SPRG3  0000000000000000 EAR
>>    0000000000000000
>> TBL    0000000000000000 TBU    0000000000000000 PVR    00000000003f0201
>> SPURR  0000000000000000
>> PURR   0000000000000000 LPCR   0000000000007005 MMCRA  0000000000000000 PPR
>>    0000000000000000
>> UMMCR0 0000000000000000 UPMC1  0000000000000000 UPMC2  0000000000000000
>> USIAR  0000000000000000
>> UMMCR1 0000000000000000 UPMC3  0000000000000000 UPMC4  0000000000000000
>> PMC5   0000000000000000
>> PMC6   0000000000000000 MMCR0  0000000000000000 PMC1   0000000000000000
>> PMC2   0000000000000000
>> SIAR   0000000000000000 MMCR1  0000000000000000 PMC3   0000000000000000
>> PMC4   0000000000000000
>> IABR   0000000000000000 DABR   0000000000000000 ICTC   0000000000000000 PIR
>>    0000000000000000
>>
>>
>>
>>
>>
>> Special purpose registers:
>> SPR:    1 (001) XER      swr uwr
>> SPR:    8 (008) LR       swr uwr
>> SPR:    9 (009) CTR      swr uwr
>> SPR:   12 (00c) UAMR     swr uwr
>> SPR:   17 (011) DSCR     swr u--
>> SPR:   18 (012) DSISR    swr u--
>> SPR:   19 (013) DAR      swr u--
>> SPR:   22 (016) DECR     swr u--
>> SPR:   25 (019) SDR1     swr u--
>> SPR:   26 (01a) SRR0     swr u--
>> SPR:   27 (01b) SRR1     swr u--
>> SPR:   28 (01c) CFAR     swr u--
>> SPR:   29 (01d) AMR      swr u--
>> SPR:  136 (088) CTRLF    s-r u--
>> SPR:  152 (098) CTRLT    sw- u--
>> SPR:  157 (09d) UAMOR    swr u--
>> SPR:  256 (100) VRSAVE   swr uwr
>> SPR:  268 (10c) TBL      s-r u-r
>> SPR:  269 (10d) TBU      s-r u-r
>> SPR:  272 (110) SPRG0    swr u--
>> SPR:  273 (111) SPRG1    swr u--
>> SPR:  274 (112) SPRG2    swr u--
>> SPR:  275 (113) SPRG3    swr u--
>> SPR:  282 (11a) EAR      swr u--
>> SPR:  284 (11c) TBL      swr u-r
>> SPR:  285 (11d) TBU      swr u-r
>> SPR:  287 (11f) PVR      s-r u--
>> SPR:  308 (134) SPURR    s-r u-r
>> SPR:  309 (135) PURR     s-r u-r
>> SPR:  318 (13e) LPCR     swr u--
>> SPR:  770 (302) MMCRA    swr u--
>> SPR:  896 (380) PPR      swr uwr
>> SPR:  936 (3a8) UMMCR0   s-r u-r
>> SPR:  937 (3a9) UPMC1    s-r u-r
>> SPR:  938 (3aa) UPMC2    s-r u-r
>> SPR:  939 (3ab) USIAR    s-r u-r
>> SPR:  940 (3ac) UMMCR1   s-r u-r
>> SPR:  941 (3ad) UPMC3    s-r u-r
>> SPR:  942 (3ae) UPMC4    s-r u-r
>> SPR:  945 (3b1) PMC5     swr u--
>> SPR:  946 (3b2) PMC6     swr u--
>> SPR:  952 (3b8) MMCR0    swr u--
>> SPR:  953 (3b9) PMC1     swr u--
>> SPR:  954 (3ba) PMC2     swr u--
>> SPR:  955 (3bb) SIAR     s-r u--
>> SPR:  956 (3bc) MMCR1    swr u--
>> SPR:  957 (3bd) PMC3     swr u--
>> SPR:  958 (3be) PMC4     swr u--
>> SPR: 1010 (3f2) IABR     swr u--
>> SPR: 1013 (3f5) DABR     swr u--
>> SPR: 1019 (3fb) ICTC     swr u--
>> SPR: 1023 (3ff) PIR      swr u--
>>
>>
>> Which is nicer/more useful?

You're comparing apples to oranges. One is printing values, one is
printing configuration - and IIRC only for some hidden debug #ifdef.

I'd suggest to sit down with Peter and discuss whether it may make sense
to turn this SPR register configuration dump into an HMP command and in
this case coordinate the command naming with ARM, where there's similar
dynamically configured cp15 registers that may need inspection.
(But if you do, just don't expect this to be picked up by next week!)

Cheers,
Andreas

>> The characters at the end tell what handler (read/write, oea/uea) is
>> defined for SPR.

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